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ez-usb fx2lp? usb microcontrolle r cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-08032 rev. *k revised january 26, 2006 1.0 features (cy7c68013a/14a/15a/16a) ? usb 2.0?usb-if high speed certified (tid # 40440111) ? single-chip integrated usb 2.0 transceiver, smart sie, and enhanced 8051 microprocessor ? fit, form and function compatible with the fx2 ? pin-compatible ? object-code-compatible ? functionally-compatible (fx2lp is a superset) ? ultra low power: i cc no more than 85 ma in any mode ? ideal for bus and battery powered applications ? software: 8051 code runs from: ? internal ram, which is downloaded via usb ? internal ram, which is loaded from eeprom ? external memory device (128 pin package) ? 16 kbytes of on-chip code/data ram ? four programmable bulk/interrupt/isochro- nous endpoints ? buffering options: double, triple, and quad ? additional prog rammable (bulk/in terrupt) 64-byte endpoint ? 8- or 16-bit external data interface ? smart media standard ecc generation ? gpif (general programmable interface) ? allows direct connection to most parallel interface ? programmable waveform descriptors and configu- ration registers to define waveforms ? supports multiple ready (rdy) inputs and control (ctl) outputs ? integrated, industry-standard enhanced 8051 ? 48-mhz, 24-mhz, or 12-mhz cpu operation ? four clocks per instruction cycle ? two usarts ? three counter/timers ? expanded interrupt system ? two data pointers ? 3.3v operation with 5v tolerant inputs ? vectored usb interrupts and gpif/fifo interrupts ? separate data buffers for th e set-up and data portions of a control transfer ? integrated i 2 c controller, runs at 100 or 400 khz ? four integrated fifos ? integrated glue logic and fifos lower system cost ? automatic conversion to and from 16-bit buses ? master or slave operation ? uses external clock or asynchronous strobes ? easy interface to asic and dsp ics ? available in commercial an d industrial temperature grade (all packages except vfbga) address (16) x20 pll /0.5 /1.0 /2.0 8051 core 12/24/48 mhz, four clocks/cycle i 2 c vcc 1.5k d+ d? address (16) / data bus (8) fx2lp gpif cy smart usb 1.1/2.0 engine usb 2.0 xcvr 16 kb ram 4 kb fifo integrated full- and high-speed xcvr additional i/os (24) addr (9) ctl (6) rdy (6) 8/16 data (8) 24 mhz ext. xtal enhanced usb core simplifies 8051 code ?soft configuration? easy firmware changes fifo and endpoint memory (master or slave operation) up to 96 mbytes/s burst rate general programmable i/f to asic/dsp or bus standards such as atapi, epp, etc. abundant i/o including two usarts high-performance micro using standard tools with lower-power options master figure 1-1. block diagram connected for full speed ecc
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 2 of 60 1.1 features (cy7c68013a/14a only) ? cy7c68014a: ideal for battery powered applications ? suspend current: 100 a (typ) ? cy7c68013a: ideal for non-battery powered applica- tions ? suspend current: 300 a (typ) ? available in five lead-free packages with up to 40 gpios ? 128-pin tqfp (40 gpios), 100-pin tqfp (40 gpios), 56-pin qfn (24 gpios), 56-pin ssop (24 gpios), and 56-pin vfbga (24 gpios) 1.2 features (cy7c68015a/16a only) ? CY7C68016A: ideal for battery powered applications ? suspend current: 100 a (typ) ? cy7c68015a: ideal for non-battery powered applica- tions ? suspend current: 300 a (typ) ? available in lead-free 56-pin qfn package (26 gpios) ? 2 more gpios than cy7c68013a/14a enabling addi- tional features in same footprint cypress semiconductor corporation?s (cypress?s) ez-usb fx2lp ? (cy7c68013a/14a) is a low-power version of the ez-usb fx2 ? (cy7c68013), which is a highly integrated, low-power usb 2.0 microcontrolle r. by integrating the usb 2.0 transceiver, serial interface engine (sie), enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, cypress has created a very cost-effective solution that provides superior time-to-market advantages with low power to enable bus powered applications. the ingenious architecture of fx2lp results in data transfer rates of over 53 mbytes per second, the maximum-allowable usb 2.0 bandwidth, while still using a low-cost 8051 microcon- troller in a package as small as a 56 vfbga (5mm x 5mm). because it incorporates the usb 2.0 transceiver, the fx2lp is more economical, providing a smaller footprint solution than usb 2.0 sie or external tran sceiver implementations. with ez-usb fx2lp, the cypress smart sie handles most of the usb 1.1 and 2.0 protocol in hardware, freeing the embedded microcontroller for applicat ion-specific functions and decreasing development time to ensure usb compatibility. the general programmable interface (gpif) and master/slave endpoint fifo (8 - or 16-bit data bus) provides an easy and glueless interface to popular interfaces such as ata, utopia, epp, pcmcia, and most dsp/processors. the fx2lp draws considerably less current than the fx2 (cy7c68013), has double the on-chip code/data ram and is fit, form and function compatible with the 56-, 100-, and 128-pin fx2. five packages are defined for the family: 56vf bga, 56 ssop, 56 qfn, 100 tqfp, and 128 tqfp. 2.0 applications ? portable video recorder ? mpeg/tv conversion ? dsl modems ? ata interface ? memory card readers ? legacy conversion devices ? cameras ? scanners ? home pna ? wireless lan ? mp3 players ? networking the ?reference designs? section of the cypress web site provides additional tools for typical usb 2.0 applications. each reference design comes complete with firmware source and object code, schematics, and documentation. please visit http://www.cypre ss.com for more information.
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 3 of 60 3.0 functional overview 3.1 usb signaling speed fx2lp operates at tw o of the three rates defined in the usb specification revision 2.0, dated april 27, 2000: ? full speed, with a signaling bit rate of 12 mbps ? high speed, with a signaling bit rate of 480 mbps. fx2lp does not support the low-speed signaling mode of 1.5 mbps. 3.2 8051 microprocessor the 8051 microprocessor embedded in the fx2lp family has 256 bytes of register ram, an expanded interrupt system, three timer/counters, and two usarts. 3.2.1 8051 clock frequency fx2lp has an on-chip oscillator circuit that uses an external 24-mhz (100-ppm) crystal with the following characteristics: ? parallel resonant ? fundamental mode ? 500- w drive level ? 12-pf (5% tolerance) load capacitors. an on-chip pll multiplies the 24-mhz oscillator up to 480 mhz, as required by the transceiver/phy, and internal counters divide it down for use as the 8051 clock. the default 8051 clock frequency is 12 mhz. the clock frequency of the 8051 can be changed by the 8051 through the cpucs register, dynamically. the clkout pin, which can be three-stated and inverted using internal cont rol bits, outputs the 50% duty cycle 8051 clock, at the selected 8051 clock frequency?48, 24, or 12 mhz. 3.2.2 usarts fx2lp contains two standard 8051 usarts, addressed via special function register (sfr) bits. the usart interface pins are available on separate i/o pins, and are not multi- plexed with port pins. uart0 and uart1 can operate using an internal clock at 230 kbaud with no more than 1% baud rate error. 230-kbaud operation is achieved by an internally derived clock source that generates overflow pulses at the appropriate time. the internal clock adjusts for the 8051 clock rate (48, 24, 12 mhz) such that it always pres ents the correct frequency for 230-kbaud operation. [1] 3.2.3 special function registers certain 8051 sfr addresses are populated to provide fast access to critical fx2lp functions. these sfr additions are shown in table 3-1 . bold type indicates non-standard, enhanced 8051 registers. the two sfr rows that end with ?0? and ?8? contain bit-addressable registers. the four i/o ports a?d use the sfr addresses used in the standard 8051 for ports 0?3, which are not implemented in fx2lp. because of the faster and more efficient sfr addressing, the fx2lp i/o ports are not addressable in external ram space (using the movx instruction). 3.3 i 2 c bus fx2lp supports the i 2 c bus as a master only at 100-/400-khz. scl and sda pins have open-drain outputs and hysteresis inputs. these signals must be pulled up to 3.3v, even if no i 2 c device is connected. 3.4 buses all packages: 8- or 16-bit ?fifo? bidirectional data bus, multi- plexed on i/o ports b and d. 128-pin package: adds 16-bit output-only 8051 address bus, 8- bit bidirectional data bus. figure 3-1. crystal configuration 12 pf 12 pf 24 mhz 20 pll c1 c2 12-pf capacitor values assumes a trace capacitance of 3 pf per side on a four-layer fr4 pca note: 1. 115-kbaud operation is also possible by programming the 8051 sm od0 or smod1 bits to a ?1? for uart0 and/or uart1, respectivel y.
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 4 of 60 3.5 usb boot methods during the power-up sequence, internal logic checks the i 2 c port for the connection of an eeprom whose first byte is either 0xc0 or 0xc2. if found, it uses the vi d/pid/did values in the eeprom in place of the in ternally stored values (0xc0), or it boot-loads the eeprom c ontents into internal ram (0xc2). if no eeprom is detect ed, fx2lp enumerates using internally stored descriptors. the default id values for fx2lp are vid/pid/did (0x04b4, 0x8613, 0xaxxx where xxx = chip revision). [2] 3.6 renumeration? because the fx2lp?s configuration is soft, one chip can take on the identities of multip le distinct usb devices. when first plugged into usb, the fx2lp enumerates automat- ically and downloads firmware and usb descriptor tables over the usb cable. next, the fx2lp enumerates again, this time as a device defined by the downloaded information. this patented two-step process, called renumeration ? , happens instantly when the device is plugged in, with no hint that the initial download step has occurred. two control bits in the usbcs (usb control and status) register control the renume ration process: discon and renum. to simulate a usb disconnect, the firmware sets discon to 1. to reconnect, the firmware clears discon to 0. before reconnecting, the firmware sets or clears the renum bit to indicate whether the firmware or the default usb device will handle device requests over endpoint zero: if renum = 0, the default usb device will handle device requests; if renum = 1, the firmware will. 3.7 bus-powered applications the fx2lp fully supports bus-powered designs by enumer- ating with less than 100 ma as required by the usb 2.0 speci- fication. 3.8 interrupt system 3.8.1 int2 interrupt request and enable registers fx2lp implements an autovector feature for int2 and int4. there are 27 int2 (usb) vectors, and 14 int4 (fifo/gpif) vectors. see ez-usb technical reference manual (trm) for more details. 3.8.2 usb-interrupt autovectors the main usb interrupt is shared by 27 interrupt sources. to save the code and processing ti me that normally would be required to identify the individual usb interrupt source, the fx2lp provides a second level of interrupt vectoring, called autovectoring. when a usb inte rrupt is asserted, the fx2lp pushes the program counter onto its stack then jumps to address 0x0043, where it expects to find a ?jump? instruction to the usb interrupt service routine. table 3-1. special function registers x8x 9x ax bx cxdxexfx 0 ioa iob ioc iod scon1 psw acc b 1sp exif int2clr ioe sbuf1 2dpl0 mpage int4clr oea 3dph0 oeb 4 dpl1 oec 5 dph1 oed 6 dps oee 7pcon 8 tcon scon0 ie ip t2con eicon eie eip 9 tmod sbuf0 atl0 autoptrh1 ep2468stat ep01stat rcap2l btl1 autoptrl1 ep24fifoflgs gpiftrig rcap2h cth0 reserved ep68fifoflgs tl2 dth1 autoptrh2 gpifsgldath th2 e ckcon autoptrl2 gpifsgldatlx f reserved autoptrset-up gpifsgldatlnox table 3-2. default id values for fx2lp default vid/pid/did vendor id 0x04b4 cypress semiconductor product id 0x8613 ez-usb fx2lp device release 0xannn depends on chip revision (nnn = chip revision where first silicon = 001) note: 2. the i 2 c bus scl and sda pins must be pulled up, even if an eeprom is not connected. otherwise this detect ion method does not work pro perly.
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 5 of 60 the fx2lp jump instruction is encoded as follows. if autovectoring is enabled (av2en = 1 in the intset-up register), the fx2lp substitutes its int2vec byte. therefore, if the high byte (?page?) of a jump-table address is preloaded at location 0x0044, the autom atically-inserted int2vec byte at 0x0045 will direct the jump to the correct address out of the 27 addresses within the page. 3.8.3 fifo/gpif interrupt (int4) just as the usb interrupt is shared among 27 individual usb-interrupt sources, the fi fo/gpif interrupt is shared among 14 individual fifo/gpif sources. the fifo/gpif interrupt, like the usb interrupt, can employ autovectoring. table 3-4 shows the priority and int4vec values for the 14 fifo/gpif interrupt sources. table 3-3. int2 usb interrupts usb interrupt table for int2 priority int2vec value source notes 1 00 sudav set-up data available 2 04 sof start of frame (or microframe) 3 08 sutok set-up token received 4 0c suspend usb suspend request 5 10 usb reset bus reset 6 14 hispeed entered hi gh speed operation 7 18 ep0ack fx2lp ack?d the control handshake 8 1c reserved 9 20 ep0-in ep0-in ready to be loaded with data 10 24 ep0-out ep0-out has usb data 11 28 ep1-in ep1-in ready to be loaded with data 12 2c ep1-out ep1-out has usb data 13 30 ep2 in: buffer available. out: buffer has data 14 34 ep4 in: buffer available. out: buffer has data 15 38 ep6 in: buffer available. out: buffer has data 16 3c ep8 in: buffer available. out: buffer has data 17 40 ibn in-bulk-nak (any in endpoint) 18 44 reserved 19 48 ep0ping ep0 out was pinged and it nak?d 20 4c ep1ping ep1 out was pinged and it nak?d 21 50 ep2ping ep2 out was pinged and it nak?d 22 54 ep4ping ep4 out was pinged and it nak?d 23 58 ep6ping ep6 out was pinged and it nak?d 24 5c ep8ping ep8 out was pinged and it nak?d 25 60 errlimit bus errors exceeded the programmed limit 26 64 27 68 reserved 28 6c reserved 29 70 ep2isoerr iso ep2 out pid sequence error 30 74 ep4isoerr iso ep4 out pid sequence error 31 78 ep6isoerr iso ep6 out pid sequence error 32 7c ep8isoerr iso ep8 out pid sequence error
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 6 of 60 if autovectoring is enabled (av4en = 1 in the intset-up register), the fx 2lp substitutes its int4vec byte. therefore, if the high byte (?page?) of a jump-table address is preloaded at location 0x0054, the autom atically-inserted int4vec byte at 0x0055 will direct the jump to the correct address out of the 14 addresses within the page. when the isr occurs, the fx2lp pushes the program count er onto its stack then jumps to address 0x0053, where it expects to find a ?jump? instruction to the isr interrupt service routine. 3.9 reset and wakeup 3.9.1 reset pin the input pin, reset#, will reset the fx2lp when asserted. this pin has hysteresis and is active low. when a crystal is used with the cy7c680xxa the reset period must allow for the stabilization of the crystal and the pll. this reset period should be approximately 5 ms after vcc has reached 3.0v. if the crystal input pin is driven by a clock signal the internal pll stabilizes in 200 s after vcc has reached 3.0v [3] . figure 3-2 shows a power-on reset condition and a reset applied during operation. a power-on reset is defined as the time reset is asserted while power is being applied to the circuit. a powered reset is defined to be when the fx2lp has previously been powered on and operat ing and the reset# pin is asserted. cypress provides an application note which describes and recommends power on reset implementation and can be found on the cypress web site. for mo re information on reset imple- mentation for the fx2 family of products visit the http://www.cypress.com. table 3-4. individual fi fo/gpif interrupt sources priority int4vec value source notes 1 80 ep2pf endpoint 2 programmable flag 2 84 ep4pf endpoint 4 programmable flag 3 88 ep6pf endpoint 6 programmable flag 4 8c ep8pf endpoint 8 programmable flag 5 90 ep2ef endpoint 2 empty flag 6 94 ep4ef endpoint 4 empty flag 7 98 ep6ef endpoint 6 empty flag 8 9c ep8ef endpoint 8 empty flag 9 a0 ep2ff endpoint 2 full flag 10 a4 ep4ff endpoint 4 full flag 11 a8 ep6ff endpoint 6 full flag 12 ac ep8ff endpoint 8 full flag 13 b0 gpifdone gpif operation complete 14 b4 gpifwf gpif waveform note: 3. if the external clock is powered at the same time as the cy 7c680xxa and has a stabilization wait period, it must be added to the 200 s.
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 7 of 60 3.9.2 wakeup pins the 8051 puts itself and the rest of the chip into a power-down mode by setting pcon.0 = 1. this stops the oscillator and pll. when wakeup is asserted by external logic, the oscil- lator restarts, after the pll stabilizes, and then the 8051 receives a wakeup interrupt. this applies whether or not fx2lp is connected to the usb. the fx2lp exits the power-down (usb suspend) state using one of the following methods: ? usb bus activity (if d+/d? lines are left floating, noise on these lines may indicate activity to the fx2lp and initiate a wakeup). ? external logic asserts the wakeup pin ? external logic asserts the pa3/wu2 pin. the second wakeup pin, wu2, can also be configured as a general purpose i/o pin. this allows a simple external r-c network to be used as a periodic wakeup source. note that wakeup is by default active low. 3.10 program/data ram 3.10.1 size the fx2lp has 16 kbytes of internal program/data ram, where psen#/rd# signals are inte rnally ored to allow the 8051 to access it as both program and data memory. no usb control registers appear in this space. two memory maps are shown in the following diagrams: figure 3-3 internal code memory, ea = 0 figure 3-4 external code memory, ea = 1. 3.10.2 internal c ode memory, ea = 0 this mode implements the internal 16-kbyte block of ram (starting at 0) as combined code and data memory. when external ram or rom is added, the external read and write strobes are suppressed for memo ry spaces that exist inside the chip. this allows the user to connect a 64-kbyte memory without requiring address decode s to keep clear of internal memory spaces. only the internal 16 kbytes and scratch pad 0.5 kbytes ram spaces have the following access: ? usb download ?usb upload ? set-up data pointer ?i 2 c interface boot load. 3.10.3 external code memory, ea = 1 the bottom 16 kbytes of program memory is external, and therefore the bottom 16 kbytes of internal ram is accessible only as data memory. figure 3-2. reset timing plots v il 0v 3.3v 3.0v t reset vcc reset# power on reset t reset vcc reset# v il powered reset 3.3v 0v table 3-5. reset timing values condition t reset power-on reset with crystal 5 ms power-on reset with external clock 200 s + clock stability time powered reset 200 s
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 8 of 60 figure 3-3. internal code memory, ea = 0 inside fx2lp outside fx2lp 7.5 kbytes usb regs and 4k fifo buffers (rd#,wr#) 0.5 kbytes ram data (rd#,wr#)* (ok to populate data memory here?rd#/wr# strobes are not active) 40 kbytes external data memory (rd#,wr#) (ok to populate data memory here?rd#/wr# strobes are not active) 16 kbytes ram code and data (psen#,rd#,wr#)* 48 kbytes external code memory (psen#) (ok to populate program memory here? psen# strobe is not active) *sudptr, usb upload/download, i 2 c interface boot access ffff e200 e1ff e000 3fff 0000 data code figure 3-4. external code memory, ea = 1 inside fx2lp outside fx2lp 7.5 kbytes usb regs and 4k fifo buffers (rd#,wr#) 0.5 kbytes ram data (rd#,wr#)* (ok to populate data memory here?rd#/wr# strobes are not active) 40 kbytes external data memory (rd#,wr#) (ok to populate data memory here?rd#/wr# strobes are not active) 16 kbytes ram data (rd#,wr#)* 64 kbytes external code memory (psen#) *sudptr, usb upload/download, i 2 c interface boot access ffff e200 e1ff e000 3fff 0000 data code
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 9 of 60 3.11 register addresses 3.12 endpoint ram 3.12.1 size ? 3 64 bytes (endpoints 0 and 1) ? 8 512 bytes (endpoints 2, 4, 6, 8) 3.12.2 organization ? ep0 ? bidirectional endpoint zero, 64-byte buffer ? ep1in, ep1out ? 64-byte buffers, bulk or interrupt ? ep2,4,6,8 ? eight 512-byte buffers, bulk, interrupt, or isochronous. ep4 and ep8 can be double buffered, while ep2 and 6 can be either double, triple, or quad buffered. for high-speed end- point configuration options, see figure 3-5 . 3.12.3 set-up data buffer a separate 8-byte buffer at 0xe6b8-0xe6bf holds the set-up data from a control transfer. 3.12.4 endpoint configurations (high-speed mode) endpoints 0 and 1 are the same for every configuration. endpoint 0 is the only control endpoint, and endpoint 1 can be either bulk or interrupt. the endpoint buffers can be configured in any 1 of the 12 configurations shown in the vertical columns. when operating in full-speed bulk mode only the first 64 bytes of each buffer are used. for example in high-speed, the max packet size is 512 bytes but in full-speed it is 64 bytes. even though a buffer is configured to be a 512 byte buffer, in full-speed only the first 64 bytes are used. the unused endpoint buffer space is not available for other opera- tions. an example endpoint configuration would be: ffff e800 e7bf e740 e73f e700 e6ff e500 e4ff e480 e47f e400 e200 e1ff e000 e3ff efff 2 kbytes reserved 64 bytes ep0 in/out 64 bytes reserved 8051 addressable registers reserved (128) 128 bytes gpif waveforms 512 bytes 8051 xdata ram f000 (512) reserved (512) e780 64 bytes ep1out e77f 64 bytes ep1in e7ff e7c0 4 kbytes ep2-ep8 buffers (8 x 512)
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 10 of 60 ep2?1024 double buffered; ep6?512 quad buffered (column 8). 3.12.5 default full-speed alternate settings 3.12.6 default high-speed alternate settings 64 64 64 512 512 1024 1024 1024 1024 1024 1024 1024 512 512 512 512 512 512 512 512 512 512 ep2 ep2 ep2 ep6 ep6 ep8 ep8 ep0 in&out ep1 in ep1 out figure 3-5. endpoint configuration 1024 1024 ep6 1024 512 512 ep8 512 512 ep6 512 512 512 512 ep2 512 512 ep4 512 512 ep2 512 512 ep4 512 512 ep2 512 512 ep4 512 512 ep2 512 512 512 512 ep2 512 512 512 512 ep2 512 512 1024 ep2 1024 1024 ep2 1024 1024 ep2 1024 512 512 ep6 1024 1024 ep6 512 512 ep8 512 512 ep6 512 512 512 512 ep6 1024 1024 ep6 512 512 ep8 512 512 ep6 512 512 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 1 2 3 4 5 6 7 8 9 10 11 12 table 3-6. default full -speed alternate settings [4, 5] alternate setting 0 1 2 3 ep0 64 64 64 64 ep1out 0 64 bulk 64 int 64 int ep1in 0 64 bulk 64 int 64 int ep2 0 64 bulk out (2) 64 int out (2) 64 iso out (2) ep4 0 64 bulk out (2) 64 bulk out (2) 64 bulk out (2) ep6 0 64 bulk in (2) 64 int in (2) 64 iso in (2) ep8 0 64 bulk in (2) 64 bulk in (2) 64 bulk in (2) notes: 4. ?0? means ?not implemented.? 5. ?2? means ?double buffered.? 6. even though these buffers are 64 bytes, they are reported as 512 for usb 2.0 compliance. the user must never transfer packets larger than 64 bytes to ep1. table 3-7. default high -speed altern ate settings [4, 5] alternate setting 0 1 2 3 ep0 64 64 64 64 ep1out 0 512 bulk [6] 64 int 64 int ep1in 0 512 bulk [6] 64 int 64 int ep2 0 512 bulk out (2) 512 int out (2) 512 iso out (2) ep4 0 512 bulk out (2) 512 bulk out (2) 512 bulk out (2) ep6 0 512 bulk in (2) 512 int in (2) 512 iso in (2) ep8 0 512 bulk in (2) 512 bulk in (2) 512 bulk in (2)
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 11 of 60 3.13 external fifo interface 3.13.1 architecture the fx2lp slave fifo architecture has eight 512-byte blocks in the endpoint ram that directly serve as fifo memories, and are controlled by fifo control signals (such as ifclk, slcs#, slrd, slwr, sloe , pktend, and flags). in operation, some of the eight ram blocks fill or empty from the sie, while the others are connected to the i/o transfer logic. the transfer logic takes two forms, the gpif for internally generated control signals, or the slave fifo interface for externally controlled transfers. 3.13.2 master/slave control signals the fx2lp endpoint fifos ar e implemented as eight physi- cally distinct 256x16 ram blocks. the 8051/sie can switch any of the ram blocks between two domains, the usb (sie) domain and the 8051-i/o unit domain. this switching is done virtually instantaneously, giving essentially zero transfer time between ?usb fifos? and ?slave fifos.? since they are physically the same memory, no bytes are actually transferred between buffers. at any given time, some ram bl ocks are filling/emptying with usb data under sie control, while other ram blocks are available to the 8051 and/or the i/o control unit. the ram blocks operate as single-por t in the usb domain, and dual-port in the 8051-i/o domain. the blocks can be configured as single, double, triple, or quad buffered as previ- ously shown. the i/o control unit implements either an internal-master (m for master) or external-maste r (s for slave) interface. in master (m) mode, the gp if internally controls fifoadr[1..0] to select a fifo. the rdy pins (two in the 56-pin package, six in the 100-pin and 128-pin packages) can be used as flag inputs from an external fifo or other logic if desired. the gpif can be run from either an internally derived clock or externally supplied clock (ifclk), at a rate that transfers data up to 96 megabytes/s (48-mhz ifclk with 16-bit interface). in slave (s) mode, the fx2lp accepts either an internally derived clock or externally supplied clock (ifclk, max. frequency 48 mhz) and slcs#, slrd, slwr, sloe, pktend signals from external logic. when using an external ifclk, the external clock must be present before switching to the external clock with the ifclksrc bit. each endpoint can individually be selected for byte or word operation by an internal configuration bit, an d a slave fifo output enable signal sloe enables data of the selected width. external logic must insure that the output enable signal is inactive when writing data to a slave fifo. the slave interface can also operate asynchronously, where the slrd and slwr signals act directly as strobes, rat her than a clock qualifier as in synchronous mode. the signals slrd, slwr, sloe and pktend are gated by the signal slcs#. 3.13.3 gpif and fifo clock rates an 8051 register bit selects one of two frequencies for the internally supplied interface clock: 30 mhz and 48 mhz. alter- natively, an externally supplied clock of 5 mhz?48 mhz feeding the ifclk pin can be used as the interface clock. ifclk can be configured to function as an output clock when the gpif and fifos are internally clocked. an output enable bit in the ifconfig register turns this clock output off, if desired. another bit within the ifconfig register will invert the ifclk signal whether internally or externally sourced. 3.14 gpif the gpif is a flexible 8- or 16-bit parallel interface driven by a user-programmable finite state machine. it allows the cy7c68013a/15a to perform local bus mastering, and can implement a wide variety of prot ocols such as ata interface, printer parallel port, and utopia. the gpif has six programmable control outputs (ctl), nine address outputs (gpifadrx), and six general-purpose ready inputs (rdy). the data bus width can be 8 or 16 bits. each gpif vector defines the state of the control outputs, and deter- mines what state a ready input (or multiple inputs) must be before proceeding. the gpif vector can be programmed to advance a fifo to the next data value, advance an address, etc. a sequence of the gpif vectors make up a single waveform that will be executed to perform the desired data move between the fx2lp and the external device. 3.14.1 six control out signals the 100- and 128-pin packages bring out all six control output pins (ctl0-ctl5). the 8051 programs the gpif unit to define the ctl waveforms. the 56-pin package brings out three of these signals, ctl0?ctl2. ctlx waveform edges can be programmed to make transitions as fast as once per clock (20.8 ns using a 48-mhz clock). 3.14.2 six ready in signals the 100- and 128-pin packages bring out all six ready inputs (rdy0?rdy5). the 8051 programs the gpif unit to test the rdy pins for gpif branching. the 56-pin package brings out two of these signals, rdy0?1. 3.14.3 nine gpif address out signals nine gpif address lines are available in the 100- and 128-pin packages, gpifadr[8..0]. the gpif address lines allow indexing through up to a 512-byte block of ram. if more address lines are needed, i/o port pins can be used. 3.14.4 long transfer mode in master mode, the 8051 approp riately sets gpif transaction count registers (gpiftcb3, gpiftcb2, gpiftcb1, or gpiftcb0) for unattended transfers of up to 2 32 transactions. the gpif automatically throttles data flow to prevent under or overflow until the full num ber of requested transactions complete. the gpif decrements the value in these registers to represent the current status of the transaction.
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 12 of 60 3.15 ecc generation [7] the ez-usb can calculate eccs (error-correcting codes) on data that passes across its gpif or slave fifo interfaces. there are two ecc configurations: two eccs, each calcu- lated over 256 bytes (smartmedia standard); and one ecc calculated over 512 bytes. the ecc can correct any one-bit error or detect any two-bit error. 3.15.1 ecc implementation the two ecc configurations ar e selected by the eccm bit: 3.15.1.1 eccm = 0 two 3-byte eccs, each calculated over a 256-byte block of data. this configuration conforms to the smartmedia standard. write any value to eccreset, then pass data across the gpif or slave fifo interface. the ecc for the first 256 bytes of data will be calculated and stored in ecc1. the ecc for the next 256 bytes will be stored in ecc2. after the second ecc is calculated, the values in the eccx registers will not change until eccreset is written again, even if more data is subse- quently passed across the interface. 3.15.1.2 eccm = 1 one 3-byte ecc calculated over a 512-byte block of data. write any value to eccreset then pass data across the gpif or slave fifo interface. the ecc for the first 512 bytes of data will be calculated and stored in ecc1; ecc2 is unused. after the ecc is calculated, t he value in ecc1 will not change until eccreset is written again, even if more data is subse- quently passed across the interface 3.16 usb uploads and downloads the core has the ability to directly edit the data contents of the internal 16-kbyte ram and of the internal 512-byte scratch pad ram via a vendor-specific command. this capability is normally used when ?soft? downloading user code and is available only to and from internal ram, only when the 8051 is held in reset. the available ram spaces are 16 kbytes from 0x0000?0x3fff (code/data) and 512 bytes from 0xe000?0xe1ff (scratch pad data ram). [8] 3.17 autopointer access fx2lp provides two identical autopointers. they are similar to the internal 8051 data pointers, but with an additional feature: they can optionally increment after every memory access. this capability is available to and from both internal and external ram. the autopointers are available in external fx2lp registers, under control of a mode bit (autoptrset-up.0). using the external fx2lp autopointer access (at 0xe67b ? 0xe67c) allows the autopointer to access all ram, internal and external to the part. also, the autopointers can point to any fx2lp register or endpoint buffer space. when autopointer access to external memory is enabled, location 0xe67b and 0xe67c in xdata and code space cannot be used. 3.18 i 2 c controller fx2lp has one i 2 c port that is driven by two internal controllers, one that automatica lly operates at boot time to load vid/pid/did and configur ation information, and another that the 8051, once running, uses to control external i 2 c devices. the i 2 c port operates in master mode only. 3.18.1 i 2 c port pins the i 2 c pins scl and sda must have external 2.2-k ? pull-up resistors even if no eeprom is connected to the fx2lp. external eeprom device addr ess pins must be configured properly. see table 3-8 for configuring the device address pins. 3.18.2 i 2 c interface boot load access at power-on reset the i 2 c interface boot loader will load the vid/pid/did configuration by tes and up to 16 kbytes of program/data. the available ram spaces are 16 kbytes from 0x0000?0x3fff and 512 bytes from 0xe000?0xe1ff. the 8051 will be in reset. i 2 c interface boot loads only occur after power-on reset. 3.18.3 i 2 c interface general-purpose access the 8051 can control peripherals connected to the i 2 c bus using the i2ctl and i2dat r egisters. fx2lp provides i 2 c master control only, it is never an i 2 c slave. 3.19 compatible with previous generation ez-usb fx2 the ez-usb fx2lp is form/fit and with minor exceptions functionally compatible with its predecessor, the ez-usb fx2. this makes for an easy transition for designers wanting to upgrade their systems from the fx2 to the fx2l p. the pinout and package selection are identical, and the vast majority of firmware previously developed for the fx2 will function in the fx2lp. for designers migrating from the fx2 to the fx2lp a change in the bill of material and review of the memory allocation (due to increased internal memory) is required for more information about migrating from ez-usb fx2 to ez-usb fx2lp, please see further details in the application note titled migrating from ez-usb fx2 to ez-usb fx2lp , which is available on the cypress website. notes: 7. to use the ecc logic, the gpif or slave fifo interface must be configured for byte-wide operation. 8. after the data has been downloaded from the host, a ?loader? can execute from internal ram in order to transfer downloaded da ta to external memory. 9. this eeprom does not have address pins. table 3-8. strap boot eepr om address li nes to these values bytes example eeprom a2 a1 a0 16 24lc00 [9] n/a n/a n/a 128 24lc01 0 0 0 256 24lc02 0 0 0 4k 24lc32 0 0 1 8k 24lc64 0 0 1 16k 24lc128 0 0 1
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 13 of 60 3.20 cy7c68013a/14a and cy7c68015a/16a differences cy7c68013a is identical to cy7c68014a in form, fit, and functionality. cy7c68015a is identical to CY7C68016A in form, fit, and functionality. cy7c68014a and CY7C68016A have a lower suspend current than cy7c68013a and cy7c68015a respectively. cy7c68014a and CY7C68016A have a lower suspend current than cy7c68013a and cy7c68015a respectively: hence are ideal for power-sensitive battery applications. cy7c68015a and CY7C68016A are available in 56-pin qfn package only. two additional gpio signals are available on the cy7c68015a and CY7C68016A to provide more flexibility when neither ifclk or clkout are needed in the 56-pin package. the usb developers who want to convert their fx2 56-pin application to a bus-pow ered system will directly benefit from these additional signals. the two gpios will give these developers the signals they need for the power control circuitry of their bus-powered application without pushing them to a high-pincount version of fx2lp. the cy7c68015a is only available in the 56-pin qfn package table 3-9. part number conversion table ez-usb fx2 part number ez-usb fx2lp part number package description cy7c68013-56pvc cy7c68013a-56pvxc or cy7c68014a-56pvxc 56-pin ssop cy7c68013-56pvct cy7c68013a-56pvxct or cy7c68014a-56pvxct 56-pin ssop ? tape and reel cy7c68013-56lfc cy7c68013a-56lfxc or cy7c68014a-56lfxc 56-pin qfn cy7c68013-100ac cy7c68013a-100axc or cy7c68014a-100axc 100-pin tqfp cy7c68013-128ac cy7c68013a-128axc or cy7c68014a-128axc 128-pin tqfp table 3-10. cy7c68013a/14a and cy7c68015a/16a pin differences cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A ifclk pe0/t0out clkout pe1/t1out
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 14 of 60 4.0 pin assignments figure 4-1 identifies all signals for the five package types. the following pages illustrate the individual pin diagrams, plus a combination diagram showing whic h of the full set of signals are available in the 128-, 100-, and 56-pin packages. the signals on the left edge of the 56-pin package in figure 4-1 are common to all versions in the fx2lp family with the noted differences between the cy7c68013a and the cy7c68015a. three modes are available in all package versions: port, gpif master, and slave fifo. these modes define the signals on the right edge of the diagram. the 8051 selects the interface mode using the ifconfig[1:0] register bits. port mode is the powe r-on default configuration. the 100-pin package adds functionality to the 56-pin package by adding these pins: ? portc or alternate gpifadr[7:0] address signals ? porte or alternate gpifadr[8] address signal and seven additional 8051 signals ? three gpif control signals ? four gpif ready signals ? nine 8051 signals (two usarts, three timer inputs, int4,and int5#) ? bkpt, rd#, wr#. the 128-pin package adds the 8051 address and data buses plus control signals. note that two of the required signals, rd# and wr#, are present in the 100-pin version. in the 100-pin and 128-pin versions, an 8051 control bit can be set to pulse the rd# and wr# pins when the 8051 reads from/writes to portc. this feature is enabled by setting portcstb bit in cpucs register. section 10.5 displays the timing diagram of the read and write strobing function on accessing portc.
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 15 of 60 rdy0 rdy1 ctl0 ctl1 ctl2 int0#/pa0 int1#/pa1 pa2 wu2/pa3 pa4 pa5 pa6 pa7 56 bkpt portc7/gpifadr7 portc6/gpifadr6 portc5/gpifadr5 portc4/gpifadr4 portc3/gpifadr3 portc2/gpifadr2 portc1/gpifadr1 portc0/gpifadr0 pe7/gpifadr8 pe6/t2ex pe5/int6 pe4/rxd1out pe3/rxd0out pe2/t2out pe1/t1out pe0/t0out rxd0 txd0 rxd1 txd1 int4 int5# t2 t1 t0 100 d7 d6 d5 d4 d3 d2 d1 d0 ea 128 rd# wr# cs# oe# psen# a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 xtalin xtalout reset# wakeup# scl sda **pe0/t0out **pe1/t1out ifclk clkout dplus dminus fd[15] fd[14] fd[13] fd[12] fd[11] fd[10] fd[9] fd[8] fd[7] fd[6] fd[5] fd[4] fd[3] fd[2] fd[1] fd[0] slrd slwr flaga flagb flagc int0#/ pa0 int1#/ pa1 sloe wu2/pa3 fifoadr0 fifoadr1 pktend pa7/flagd/slcs# fd[15] fd[14] fd[13] fd[12] fd[11] fd[10] fd[9] fd[8] fd[7] fd[6] fd[5] fd[4] fd[3] fd[2] fd[1] fd[0] pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 int0#/pa0 int1#/pa1 pa2 wu2/pa3 pa4 pa5 pa6 pa7 port gpif master slave fifo ctl3 ctl4 ctl5 rdy2 rdy3 rdy4 rdy5 figure 4-1. signals ** pinout for cy7c68015a/ cy7c680 16a only **pe0 replaces ifclk on cy7c68015a & pe1 replaces clkout
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 16 of 60 clkout vcc gnd rdy0/*slrd rdy1/*slwr rdy2 rdy3 rdy4 rdy5 avcc xtalout xtalin agnd nc nc nc avcc dplus dminus agnd a11 a12 a13 a14 a15 vcc gnd int4 t0 t1 t2 *ifclk reserved bkpt ea scl sda oe# pd0/fd8 *wakeup vcc reset# ctl5 a3 a2 a1 a0 gnd pa7/*flagd/slcs# pa6/*pktend pa5/fifoadr1 pa4/fifoadr0 d7 d6 d5 pa3/*wu2 pa2/*sloe pa1/int1# pa0/int0# vcc gnd pc7/gpifadr7 pc6/gpifadr6 pc5/gpifadr5 pc4/gpifadr4 pc3/gpifadr3 pc2/gpifadr2 pc1/gpifadr1 pc0/gpifadr0 ctl2/*flagc ctl1/*flagb ctl0/*flaga vcc ctl4 ctl3 gnd pd1/fd9 pd2/fd10 pd3/fd11 int5# vcc pe0/t0out pe1/t1out pe2/t2out pe3/rxd0out pe4/rxd1out pe5/int6 pe6/t2ex pe7/gpifadr8 gnd a4 a5 a6 a7 pd4/fd12 pd5/fd13 pd6/fd14 pd7/fd15 gnd a8 a9 a10 cy7c68013a/cy7c68014a 128-pin tqfp 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 vcc d4 d3 d2 d1 d0 gnd pb7/fd7 pb6/fd6 pb5/fd5 pb4/fd4 rxd1 txd1 rxd0 txd0 gnd vcc pb3/fd3 pb2/fd2 pb1/fd1 pb0/fd0 vcc cs# wr# rd# psen# figure 4-2. cy7c68013a/cy7c68014a 128-pin tqfp pin assignment * denotes programmable polarity
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 17 of 60 pd0/fd8 *wakeup vcc reset# ctl5 gnd pa7/*flagd/slcs# pa6/*pktend pa5/fifoadr1 pa4/fifoadr0 pa3/*wu2 pa2/*sloe pa1/int1# pa0/int0# vcc gnd pc7/gpifadr7 pc6/gpifadr6 pc5/gpifadr5 pc4/gpifadr4 pc3/gpifadr3 pc2/gpifadr2 pc1/gpifadr1 pc0/gpifadr0 ctl2/*flagc ctl1/*flagb ctl0/*flaga vcc ctl4 ctl3 pd1/fd9 pd2/fd10 pd3/fd11 int5# vcc pe0/t0out pe1/t1out pe2/t2out pe3/rxd0out pe4/rxd1out pe5/int6 pe6/t2ex pe7/gpifadr8 gnd pd4/fd12 pd5/fd13 pd6/fd14 pd7/fd15 gnd clkout cy7c68013a/cy7c68014a 100-pin tqfp gnd vcc gnd pb7/fd7 pb6/fd6 pb5/fd5 pb4/fd4 rxd1 txd1 rxd0 txd0 gnd vcc pb3/fd3 pb2/fd2 pb1/fd1 pb0/fd0 vcc wr# rd# 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 vcc gnd rdy0/*slrd rdy1/*slwr rdy2 rdy3 rdy4 rdy5 avcc xtalout xtalin agnd nc nc nc avcc dplus dminus agnd vcc gnd int4 t0 t1 t2 *ifclk reserved bkpt scl sda 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 figure 4-3. cy7c68013a/cy7c68014a 100-pin tqfp pin assignment * denotes programmable polarity
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 18 of 60 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 pd5/fd13 pd6/fd14 pd7/fd15 gnd clkout/t1out vcc gnd rdy0/*slrd rdy1/*slwr avcc xtalout xtalin agnd avcc dplus dminus agnd vcc gnd *ifclk/t0out reserved scl sda vcc pb0/fd0 pb1/fd1 pb2/fd2 pb3/fd3 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 pd4/fd12 pd3/fd11 pd2/fd10 pd1/fd9 pd0/fd8 *wakeup vcc reset# gnd pa7/*flagd/slcs# pa6/pktend pa5/fifoadr1 pa4/fifoadr0 pa3/*wu2 pa2/*sloe pa1/int1# pa0/int0# vcc ctl2/*flagc ctl1/*flagb ctl0/*flaga gnd vcc gnd pb7/fd7 pb6/fd6 pb5/fd5 pb4/fd4 cy7c68013a/cy7c68014a 56-pin ssop figure 4-4. cy7c68013a/cy7c68014a 56-pin ssop pin assignment * denotes programmable polarity
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 19 of 60 28 27 26 25 24 23 22 21 20 19 18 17 16 15 43 44 45 46 47 48 49 50 51 52 53 54 55 56 1 2 3 4 5 6 7 8 9 10 11 12 13 14 42 41 40 39 38 37 36 35 34 33 32 31 30 29 figure 4-5. cy7c68013a/14a/15a /16a 56-pin qfn pin assignment * denotes programmable polarity reset# gnd pa7/*flagd/slcs# pa6/*pktend pa5/fifoadr1 pa4/fifoadr0 pa3/*wu2 pa2/*sloe pa1/int1# pa0/int0# vcc ctl2/*flagc ctl1/*flagb ctl0/*flaga rdy0/*slrd rdy1/*slwr avcc xtalout xtalin agnd avcc dplus dminus agnd vcc gnd *ifclk/**pe0/t0out reserved vcc *wakeup pd0/fd8 pd1/fd9 pd2/fd10 pd3/fd11 pd4/fd12 pd5/fd13 pd6/fd14 pd7/fd15 gnd clkout/**pe1/t1out vcc gnd gnd vcc gnd pb7/fd7 pb6/fd6 pb5/fd5 pb4/fd4 pb3/fd3 pb2/fd2 pb1/fd1 pb0/fd0 vcc sda scl cy7c68013a/cy7c68014a & cy7c68015a/CY7C68016A 56-pin qfn ** denotes cy7c68015a/CY7C68016A pinout
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 20 of 60 figure 4-6. cy7c68013a 56-pin vfbga pin assignment - top view 12345678 a b c d e f g h 1a 2a 3a 4a 5a 6a 7a 8a 1b 2b 3b 4b 5b 6b 7b 8b 1c 2c 3c 4c 5c 6c 7c 8c 1d 2d 7d 8d 1e 2e 7e 8e 1f 2f 3f 4f 5f 6f 7f 8f 1g 2g 3g 4g 5g 6g 7g 8g 1h 2h 3h 4h 5h 6h 7h 8h
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 21 of 60 4.1 cy7c68013a/15a pin descriptions table 4-1. fx2lp pin descriptions [10] 128 tqfp 100 tqfp 56 ssop 56 qfn 56 vfbga name type default description 10 9 10 3 2d avcc power n/a analog vcc . connect this pin to 3.3v power source. this signal provides power to the analog section of the chip. 17 16 14 7 1d avcc power n/a analog vcc . connect this pin to 3.3v power source. this signal provides power to the analog section of the chip. 13 12 13 6 2f agnd ground n/a analog ground . connect to ground with as short a path as possible. 20 19 17 10 1f agnd ground n/a analog ground . connect to ground with as short a path as possible. 19 18 16 9 1e dminus i/o/z z usb d? signal . connect to the usb d? signal. 18 17 15 8 2e dplus i/o/z z usb d+ signal . connect to the usb d+ signal. 94 a0 output l 8051 address bus . this bus is driven at all times. when the 8051 is addressing internal ram it reflects the internal address. 95 a1 output l 96 a2 output l 97 a3 output l 117 a4 output l 118 a5 output l 119 a6 output l 120 a7 output l 126 a8 output l 127 a9 output l 128 a10 output l 21 a11 output l 22 a12 output l 23 a13 output l 24 a14 output l 25 a15 output l 59 d0 i/o/z z 8051 data bus . this bidirectional bus is high-impedance when inactive, input for bus reads, and output for bus writes. the data bus is used for external 8051 program and data memory. the data bus is active only for external bus accesses, and is driven low in suspend. 60 d1 i/o/z z 61 d2 i/o/z z 62 d3 i/o/z z 63 d4 i/o/z z 86 d5 i/o/z z 87 d6 i/o/z z 88 d7 i/o/z z 39 psen# output h program store enable . this active-low signal indicates an 8051 code fetch from external memory. it is active for program memory fetches from 0x4000?0xffff when the ea pin is low, or from 0x0000?0xffff when the ea pin is high. note: 10. unused inputs should not be left floating. tie either high or low as appropriate. outputs should only be pulled up or down t o ensure signals at power-up and in standby. note also that no pins should be driven while the device is powered down.
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 22 of 60 34 28 bkpt output l breakpoint . this pin goes active (high) when the 8051 address bus matches the bpaddrh/l registers and breakpoints are enabled in the breakpt register (bpen = 1). if the bppulse bit in the breakpt register is high, this signal pulses high for eight 12-/24-/48-mhz clocks. if the bppulse bit is low, the signal remains high until the 8051 clears the break bit (by writing 1 to it) in the breakpt register. 99 77 49 42 8b reset# input n/a active low reset . resets the entire chip. see section 3.9 ?reset and wakeup? on page 6 for more details. 35 ea input n/a external access . this pin determines where the 8051 fetches code between addresses 0x0000 and 0x3fff. if ea = 0 the 8051 fetches this code from its internal ram. if ea = 1 the 8051 fetches this code from external memory. 12 11 12 5 1c xtalin input n/a crystal input . connect this signal to a 24-mhz parallel-resonant, fundamental mode crystal and load capacitor to gnd. it is also correct to drive xtalin with an external 24-mhz square wave derived from another clock source. when driving from an external source, the driving signal should be a 3.3v square wave. 11 10 11 4 2c xtalout output n/a crystal output . connect this signal to a 24-mhz parallel-resonant, fundamental mode crystal and load capacitor to gnd. if an external clock is used to drive xtalin, leave this pin open. 1 100 5 54 2b clkout on cy7c68013a ------------------ pe1 or t1out on cy7c68015a o/z ----------- i/o/z 12 mhz ---------- i (pe1) clkout: 12-, 24- or 48-mhz clock, phase locked to the 24-mhz input clock. the 8051 defaults to 12-mhz operation. the 8051 may th ree-state this output by setting cpucs.1 = 1. ------------------------------------------------------------------------ multiplexed pin whose function is selected by the portecfg.0 bit. pe1 is a bidirectional i/o port pin. t1out is an active-high signal from 8051 timer-counter1. t1out outputs a high level for one clkout clock cycle when timer1 overflows. if timer1 is operated in mode 3 (two separate timer/counters), t1out is active when the low byte timer/counter overflows. port a 82 67 40 33 8g pa0 or int0# i/o/z i (pa0) multiplexed pin whose function is selected by portacfg.0 pa0 is a bidirectional io port pin. int0# is the active-low 8051 int0 interrupt input signal, which is either edge triggered (it0 = 1) or level triggered (it0 = 0). 83 68 41 34 6g pa1 or int1# i/o/z i (pa1) multiplexed pin whose function is selected by: portacfg.1 pa1 is a bidirectional io port pin. int1# is the active-low 8051 int1 interrupt input signal, which is either edge triggered (it1 = 1) or level triggered (it1 = 0). table 4-1. fx2lp pin descriptions (continued) [10] 128 tqfp 100 tqfp 56 ssop 56 qfn 56 vfbga name type default description
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 23 of 60 84 69 42 35 8f pa2 or sloe or i/o/z i (pa2) multiplexed pin whose function is selected by two bits: ifconfig[1:0]. pa2 is a bidirectional io port pin. sloe is an input-only output enable with program- mable polarity (fifopinpola r.4) for the slave fifos connected to fd[7..0] or fd[15..0]. 85 70 43 36 7f pa3 or wu2 i/o/z i (pa3) multiplexed pin whose function is selected by: wakeup.7 and oea.3 pa3 is a bidirectional i/o port pin. wu2 is an alternate source for usb wakeup, enabled by wu2en bit (wakeup.1) and polarity set by wu2pol (wakeup.4). if the 8051 is in suspend and wu2en = 1, a transition on this pin starts up the oscil- lator and interrupts the 8051 to allow it to exit the suspend mode. asserting this pin inhibits the chip from suspending, if wu2en = 1. 89 71 44 37 6f pa4 or fifoadr0 i/o/z i (pa4) multiplexed pin whose function is selected by: ifconfig[1..0]. pa4 is a bidirectional i/o port pin. fifoadr0 is an input-only address select for the slave fifos connected to fd[7..0] or fd[15..0]. 90 72 45 38 8c pa5 or fifoadr1 i/o/z i (pa5) multiplexed pin whose function is selected by: ifconfig[1..0]. pa5 is a bidirectional i/o port pin. fifoadr1 is an input-only address select for the slave fifos connected to fd[7..0] or fd[15..0]. 91 73 46 39 7c pa6 or pktend i/o/z i (pa6) multiplexed pin whose function is selected by the ifconfig[1:0] bits. pa6 is a bidirectional i/o port pin. pktend is an input used to commit the fifo packet data to the endpoint and whose polarity is program- mable via fifopinpolar.5. 92 74 47 40 6c pa7 or flagd or slcs# i/o/z i (pa7) multiplexed pin whose function is selected by the ifconfig[1:0] and portacfg.7 bits. pa7 is a bidirectional i/o port pin. flagd is a programmable slave-fifo output status flag signal. slcs# gates all other slave fifo enable/strobes port b 44 34 25 18 3h pb0 or fd[0] i/o/z i (pb0) multiplexed pin whose function is selected by the following bits: ifconfig[1..0]. pb0 is a bidirectional i/o port pin. fd[0] is the bidirectional fifo/gpif data bus. 45 35 26 19 4f pb1 or fd[1] i/o/z i (pb1) multiplexed pin whose function is selected by the following bits: ifconfig[1..0]. pb1 is a bidirectional i/o port pin. fd[1] is the bidirectional fifo/gpif data bus. 46 36 27 20 4h pb2 or fd[2] i/o/z i (pb2) multiplexed pin whose function is selected by the following bits: ifconfig[1..0]. pb2 is a bidirectional i/o port pin. fd[2] is the bidirectional fifo/gpif data bus. 47 37 28 21 4g pb3 or fd[3] i/o/z i (pb3) multiplexed pin whose function is selected by the following bits: ifconfig[1..0]. pb3 is a bidirectional i/o port pin. fd[3] is the bidirectional fifo/gpif data bus. table 4-1. fx2lp pin descriptions (continued) [10] 128 tqfp 100 tqfp 56 ssop 56 qfn 56 vfbga name type default description
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 24 of 60 54 44 29 22 5h pb4 or fd[4] i/o/z i (pb4) multiplexed pin whose function is selected by the following bits: ifconfig[1..0]. pb4 is a bidirectional i/o port pin. fd[4] is the bidirectional fifo/gpif data bus. 55 45 30 23 5g pb5 or fd[5] i/o/z i (pb5) multiplexed pin whose function is selected by the following bits: ifconfig[1..0]. pb5 is a bidirectional i/o port pin. fd[5] is the bidirectional fifo/gpif data bus. 56 46 31 24 5f pb6 or fd[6] i/o/z i (pb6) multiplexed pin whose function is selected by the following bits: ifconfig[1..0]. pb6 is a bidirectional i/o port pin. fd[6] is the bidirectional fifo/gpif data bus. 57 47 32 25 6h pb7 or fd[7] i/o/z i (pb7) multiplexed pin whose function is selected by the following bits: ifconfig[1..0]. pb7 is a bidirectional i/o port pin. fd[7] is the bidirectional fifo/gpif data bus. port c 72 57 pc0 or gpifadr0 i/o/z i (pc0) multiplexed pin whose function is selected by portccfg.0 pc0 is a bidirectional i/o port pin. gpifadr0 is a gpif address output pin. 73 58 pc1 or gpifadr1 i/o/z i (pc1) multiplexed pin whose function is selected by portccfg.1 pc1 is a bidirectional i/o port pin. gpifadr1 is a gpif address output pin. 74 59 pc2 or gpifadr2 i/o/z i (pc2) multiplexed pin whose function is selected by portccfg.2 pc2 is a bidirectional i/o port pin. gpifadr2 is a gpif address output pin. 75 60 pc3 or gpifadr3 i/o/z i (pc3) multiplexed pin whose function is selected by portccfg.3 pc3 is a bidirectional i/o port pin. gpifadr3 is a gpif address output pin. 76 61 pc4 or gpifadr4 i/o/z i (pc4) multiplexed pin whose function is selected by portccfg.4 pc4 is a bidirectional i/o port pin. gpifadr4 is a gpif address output pin. 77 62 pc5 or gpifadr5 i/o/z i (pc5) multiplexed pin whose function is selected by portccfg.5 pc5 is a bidirectional i/o port pin. gpifadr5 is a gpif address output pin. 78 63 pc6 or gpifadr6 i/o/z i (pc6) multiplexed pin whose function is selected by portccfg.6 pc6 is a bidirectional i/o port pin. gpifadr6 is a gpif address output pin. 79 64 pc7 or gpifadr7 i/o/z i (pc7) multiplexed pin whose function is selected by portccfg.7 pc7 is a bidirectional i/o port pin. gpifadr7 is a gpif address output pin. port d 102 80 52 45 8a pd0 or fd[8] i/o/z i (pd0) multiplexed pin whose function is selected by the ifconfig[1..0] and epxfifocfg.0 (wordwide) bits. fd[8] is the bidirectional fifo/gpif data bus. table 4-1. fx2lp pin descriptions (continued) [10] 128 tqfp 100 tqfp 56 ssop 56 qfn 56 vfbga name type default description
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 25 of 60 103 81 53 46 7a pd1 or fd[9] i/o/z i (pd1) multiplexed pin whose function is selected by the ifconfig[1..0] and epxfifocfg.0 (wordwide) bits. fd[9] is the bidirectional fifo/gpif data bus. 104 82 54 47 6b pd2 or fd[10] i/o/z i (pd2) multiplexed pin whose function is selected by the ifconfig[1..0] and epxfifocfg.0 (wordwide) bits. fd[10] is the bidirectional fifo/gpif data bus. 105 83 55 48 6a pd3 or fd[11] i/o/z i (pd3) multiplexed pin whose function is selected by the ifconfig[1..0] and epxfifocfg.0 (wordwide) bits. fd[11] is the bidirectional fifo/gpif data bus. 121 95 56 49 3b pd4 or fd[12] i/o/z i (pd4) multiplexed pin whose function is selected by the ifconfig[1..0] and epxfifocfg.0 (wordwide) bits. fd[12] is the bidirectional fifo/gpif data bus. 122 96 1 50 3a pd5 or fd[13] i/o/z i (pd5) multiplexed pin whose function is selected by the ifconfig[1..0] and epxfifocfg.0 (wordwide) bits. fd[13] is the bidirectional fifo/gpif data bus. 123 97 2 51 3c pd6 or fd[14] i/o/z i (pd6) multiplexed pin whose function is selected by the ifconfig[1..0] and epxfifocfg.0 (wordwide) bits. fd[14] is the bidirectional fifo/gpif data bus. 124 98 3 52 2a pd7 or fd[15] i/o/z i (pd7) multiplexed pin whose function is selected by the ifconfig[1..0] and epxfifocfg.0 (wordwide) bits. fd[15] is the bidirectional fifo/gpif data bus. port e 108 86 pe0 or t0out i/o/z i (pe0) multiplexed pin whose function is selected by the portecfg.0 bit. pe0 is a bidirectional i/o port pin. t0out is an active-high signal from 8051 timer-counter0. t0out outputs a high level for one clkout clock cycle when timer0 overflows. if timer0 is operated in mode 3 (two separate timer/counters), t0out is active when the low byte timer/counter overflows. 109 87 pe1 or t1out i/o/z i (pe1) multiplexed pin whose function is selected by the portecfg.1 bit. pe1 is a bidirectional i/o port pin. t1out is an active-high signal from 8051 timer-counter1. t1out outputs a high level for one clkout clock cycle when timer1 overflows. if timer1 is operated in mode 3 (two separate timer/counters), t1out is active when the low byte timer/counter overflows. 110 88 pe2 or t2out i/o/z i (pe2) multiplexed pin whose function is selected by the portecfg.2 bit. pe2 is a bidirectional i/o port pin. t2out is the active-high output signal from 8051 timer2. t2out is active (high) for one clock cycle when timer/counter 2 overflows. 111 89 pe3 or rxd0out i/o/z i (pe3) multiplexed pin whose function is selected by the portecfg.3 bit. pe3 is a bidirectional i/o port pin. rxd0out is an active-high signal from 8051 uart0. if rxd0out is selected and uart0 is in mode 0, this pin provides the output data for uart0 only when it is in sync mode. otherwise it is a 1. table 4-1. fx2lp pin descriptions (continued) [10] 128 tqfp 100 tqfp 56 ssop 56 qfn 56 vfbga name type default description
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 26 of 60 112 90 pe4 or rxd1out i/o/z i (pe4) multiplexed pin whose function is selected by the portecfg.4 bit. pe4 is a bidirectional i/o port pin. rxd1out is an active-high output from 8051 uart1. when rxd1out is selected and uart1 is in mode 0, this pin provides the output data for uart1 only when it is in sync mode. in modes 1, 2, and 3, this pin is high. 113 91 pe5 or int6 i/o/z i (pe5) multiplexed pin whose function is selected by the portecfg.5 bit. pe5 is a bidirectional i/o port pin. int6 is the 8051 int6 interrupt request input signal. the int6 pin is edge-sensitive, active high. 114 92 pe6 or t2ex i/o/z i (pe6) multiplexed pin whose function is selected by the portecfg.6 bit. pe6 is a bidirectional i/o port pin. t2ex is an active-high input signal to the 8051 timer2. t2ex reloads timer 2 on its falling edge. t2ex is active only if the exen2 bit is set in t2con. 115 93 pe7 or gpifadr8 i/o/z i (pe7) multiplexed pin whose function is selected by the portecfg.7 bit. pe7 is a bidirectional i/o port pin. gpifadr8 is a gpif address output pin. 4 3 8 1 1a rdy0 or slrd input n/a multiplexed pin whose function is selected by the following bits: ifconfig[1..0]. rdy0 is a gpif input signal. slrd is the input-only read strobe with programmable polarity (fifopinpolar.3) for the slave fifos connected to fd[7..0] or fd[15..0]. 5 4 9 2 1b rdy1 or slwr input n/a multiplexed pin whose function is selected by the following bits: ifconfig[1..0]. rdy1 is a gpif input signal. slwr is the input-only write strobe with programmable polarity (fifopinpolar.2) for the slave fifos connected to fd[7..0] or fd[15..0]. 6 5 rdy2 input n/a rdy2 is a gpif input signal. 7 6 rdy3 input n/a rdy3 is a gpif input signal. 8 7 rdy4 input n/a rdy4 is a gpif input signal. 9 8 rdy5 input n/a rdy5 is a gpif input signal. 69 54 36 29 7h ctl0 or flaga o/z h multiplexed pin whose function is selected by the following bits: ifconfig[1..0]. ctl0 is a gpif control output. flaga is a programmable slave-fifo output status flag signal. defaults to programmable for the fifo selected by the fifoadr[1:0] pins. table 4-1. fx2lp pin descriptions (continued) [10] 128 tqfp 100 tqfp 56 ssop 56 qfn 56 vfbga name type default description
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 27 of 60 70 55 37 30 7g ctl1 or flagb o/z h multiplexed pin whose function is selected by the following bits: ifconfig[1..0]. ctl1 is a gpif control output. flagb is a programmable slave-fifo output status flag signal. defaults to full for the fifo selected by the fifoadr[1:0] pins. 71 56 38 31 8h ctl2 or flagc o/z h multiplexed pin whose function is selected by the following bits: ifconfig[1..0]. ctl2 is a gpif control output. flagc is a programmable slave-fifo output status flag signal. defaults to empty for the fifo selected by the fifoadr[1:0] pins. 66 51 ctl3 o/z h ctl3 is a gpif control output. 67 52 ctl4 output h ctl4 is a gpif control output. 98 76 ctl5 output h ctl5 is a gpif control output. 32 26 20 13 2g ifclk on cy7c68013a ------------------ pe0 or t0out on cy7c68015a i/o/z ----------- i/o/z z ---------- i (pe0) interface clock, used for synchronously clocking data into or out of the slave fifos. ifclk also serves as a timing reference for all slave fifo control signals and gpif. when internal clocking is used (ifconfig.7 = 1) the ifclk pin can be config ured to output 30/48 mhz by bits ifconfig.5 and ifconfig.6. ifclk may be inverted, whether internally or externally sourced, by setting the bit ifconfig.4 =1. ----------------------------------------------------------------------- multiplexed pin whose function is selected by the portecfg.0 bit. pe0 is a bidirectional i/o port pin. t0out is an active-high signal from 8051 timer-counter0. t0out outputs a high level for one clkout clock cycle when timer0 overflows. if timer0 is operated in mode 3 (two separate timer/counters), t0out is active when the low byte timer/counter overflows. 28 22 int4 input n/a int4 is the 8051 int4 interrupt request input signal. the int4 pin is edge-sensitive, active high. 106 84 int5# input n/a int5# is the 8051 int5 interrupt request input signal. the int5 pin is edge-sensitive, active low. 31 25 t2 input n/a t2 is the active-high t2 inpu t signal to 8051 timer2, which provides the input to timer2 when c/t2 = 1. when c/t2 = 0, timer2 does not use this pin. 30 24 t1 input n/a t1 is the active-high t1 signal for 8051 timer1, which provides the input to timer1 when c/t1 is 1. when c/t1 is 0, timer1 does not use this bit. 29 23 t0 input n/a t0 is the active-high t0 signal for 8051 timer0, which provides the input to timer0 when c/t0 is 1. when c/t0 is 0, timer0 does not use this bit. 53 43 rxd1 input n/a rxd1 is an active-high input signal for 8051 uart1, which provides data to the uart in all modes. 52 42 txd1 output h txd1 is an active-high output pin from 8051 uart1, which provides the output clock in sync mode, and the output data in async mode. table 4-1. fx2lp pin descriptions (continued) [10] 128 tqfp 100 tqfp 56 ssop 56 qfn 56 vfbga name type default description
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 28 of 60 51 41 rxd0 input n/a rxd0 is the active-high rxd0 input to 8051 uart0, which provides data to the uart in all modes. 50 40 txd0 output h txd0 is the active-high txd0 output from 8051 uart0, which provides the output clock in sync mode, and the output data in async mode. 42 cs# output h cs# is the active-low chip se lect for external memory. 41 32 wr# output h wr# is the active-low write strobe output for external memory. 40 31 rd# output h rd# is the active-low read st robe output for external memory. 38 oe# output h oe# is the active-low output enable for external memory. 33 27 21 14 2h reserved input n/a reserved . connect to ground. 101 79 51 44 7b wakeup input n/a usb wakeup . if the 8051 is in suspend, asserting this pin starts up the oscillator and interrupts the 8051 to allow it to exit the suspend mode. holding wakeup asserted inhibits the ez-usb ? chip from suspending. this pin has programmable polarity (wakeup.4). 36 29 22 15 3f scl od z clock for the i 2 c interface. connect to vcc with a 2.2k resistor, even if no i 2 c peripheral is attached. 37 30 23 16 3g sda od z data for i 2 c-compatible interface . connect to vcc with a 2.2k resistor, even if no i 2 c-compatible peripheral is attached . 216555avcc powern/a vcc . connect to 3.3v power source. 26 20 18 11 1g vcc power n/a vcc . connect to 3.3v power source. 43 33 24 17 7e vcc power n/a vcc . connect to 3.3v power source. 48 38 vcc power n/a vcc . connect to 3.3v power source. 64 49 34 27 8e vcc power n/a vcc . connect to 3.3v power source. 68 53 vcc power n/a vcc . connect to 3.3v power source. 81 66 39 32 5c vcc power n/a vcc . connect to 3.3v power source. 100 78 50 43 5b vcc power n/a vcc . connect to 3.3v power source. 107 85 vcc power n/a vcc . connect to 3.3v power source. 3 2 7 56 4b gnd ground n/a ground . 27 21 19 12 1h gnd ground n/a ground . 49 39 gnd ground n/a ground . 58 48 33 26 7d gnd ground n/a ground . 65 50 35 28 8d gnd ground n/a ground . 80 65 gnd ground n/a ground . 93 75 48 41 4c gnd ground n/a ground . 116 94 gnd ground n/a ground . 125 99 4 53 4a gnd ground n/a ground . 14 13 nc n/a n/a no connect . this pin must be left open. 15 14 nc n/a n/a no connect . this pin must be left open. 16 15 nc n/a n/a no connect . this pin must be left open. table 4-1. fx2lp pin descriptions (continued) [10] 128 tqfp 100 tqfp 56 ssop 56 qfn 56 vfbga name type default description
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 29 of 60 5.0 register summary fx2lp register bit definitions are describ ed in the fx2lp trm in greater detail. table 5-1. fx2lp register summary hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access gpif waveform memories e400 128 wavedata gpif waveform descriptor 0, 1, 2, 3 data d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw e480 128 reserved general configuration e50d gpcr2 general purpose configu- ration register 2 reserved reserved reserved full_spee d_only reserved reserved reserved reserved 00000000 r e600 1 cpucs cpu control & status 0 0 portcstb clkspd1 clkspd0 clkinv clkoe 8051res 00000010 rrbbbbbr e601 1 ifconfig interface configuration (ports, gpif, slave fifos) ifclksrc 3048mhz ifclkoe ifclkpol async gstate ifcfg1 ifcfg0 10000000 rw e602 1 pinflagsab [11] slave fifo flaga and flagb pin configuration flagb3 flagb2 flagb1 flagb0 flaga3 flaga2 flaga1 flaga0 00000000 rw e603 1 pinflagscd [11] slave fifo flagc and flagd pin configuration flagd3 flagd2 flagd1 flagd0 flagc3 flagc2 flagc1 flagc0 00000000 rw e604 1 fiforeset [11] restore fifos to default state nakall 0 0 0 ep3 ep2 ep1 ep0 xxxxxxxx w e605 1 breakpt breakpoint control 0 0 0 0 break bppulse bpen 0 00000000 rrrrbbbr e606 1 bpaddrh breakpoint address h a15 a14 a13 a12 a11 a10 a9 a8 xxxxxxxx rw e607 1 bpaddrl breakpoint address l a7 a6 a5 a4 a3 a2 a1 a0 xxxxxxxx rw e608 1 uart230 230 kbaud internally generated ref. clock 0 0 0 0 0 0 230uart1 230uart0 00000000 rrrrrrbb e609 1 fifopinpolar [11] slave fifo interface pins polarity 0 0 pktend sloe slrd slwr ef ff 00000000 rrbbbbbb e60a 1 revid chip revision rv7 rv6 rv5 rv4 rv3 rv2 rv1 rv0 reva 00000001 r e60b 1 revctl [11] chip revision control 0 0 0 0 0 0 dyn_out enh_pkt 00000000 rrrrrrbb udma e60c 1 gpifholdamount mstb hold time (for udma) 0 0 0 0 0 0 holdtime1 holdtime0 00000000 rrrrrrbb 3 reserved endpoint configuration e610 1 ep1outcfg endpoint 1-out configuration valid 0 type1 type0 0 0 0 0 10100000 brbbrrrr e611 1 ep1incfg endpoint 1-in configuration valid 0 type1 type0 0 0 0 0 10100000 brbbrrrr e612 1 ep2cfg endpoint 2 configuration valid dir type1 type0 size 0 buf1 buf0 10100010 bbbbbrbb e613 1 ep4cfg endpoint 4 configuration valid dir type1 type0 0 0 0 0 10100000 bbbbrrrr e614 1 ep6cfg endpoint 6 configuration valid dir type1 type0 size 0 buf1 buf0 11100010 bbbbbrbb e615 1 ep8cfg endpoint 8 configuration valid dir type1 type0 0 0 0 0 11100000 bbbbrrrr 2 reserved e618 1 ep2fifocfg [11] endpoint 2 / slave fifo configuration 0 infm1 oep1 autoout autoin zerolenin 0 wordwide 00000101 rbbbbbrb e619 1 ep4fifocfg [11] endpoint 4 / slave fifo configuration 0 infm1 oep1 autoout autoin zerolenin 0 wordwide 00000101 rbbbbbrb e61a 1 ep6fifocfg [11] endpoint 6 / slave fifo configuration 0 infm1 oep1 autoout autoin zerolenin 0 wordwide 00000101 rbbbbbrb e61b 1 ep8fifocfg [11] endpoint 8 / slave fifo configuration 0 infm1 oep1 autoout autoin zerolenin 0 wordwide 00000101 rbbbbbrb e61c 4 reserved e620 1 ep2autoinlenh [11 endpoint 2 autoin packet length h 0 0 0 0 0 pl10 pl9 pl8 00000010 rrrrrbbb e621 1 ep2autoinlenl [11] endpoint 2 autoin packet length l pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl0 00000000 rw e622 1 ep4autoinlenh [11] endpoint 4 autoin packet length h 0 0 0 0 0 0 pl9 pl8 00000010 rrrrrrbb e623 1 ep4autoinlenl [11] endpoint 4 autoin packet length l pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl0 00000000 rw e624 1 ep6autoinlenh [11] endpoint 6 autoin packet length h 0 0 0 0 0 pl10 pl9 pl8 00000010 rrrrrbbb e625 1 ep6autoinlenl [11] endpoint 6 autoin packet length l pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl0 00000000 rw e626 1 ep8autoinlenh [11] endpoint 8 autoin packet length h 0 0 0 0 0 0 pl9 pl8 00000010 rrrrrrbb e627 1 ep8autoinlenl [11] endpoint 8 autoin packet length l pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl0 00000000 rw e628 1 ecccfg ecc configuration 0 0 0 0 0 0 0 eccm 00000000 rrrrrrrb e629 1 eccreset ecc reset x x x x x x x x 00000000 w e62a 1 ecc1b0 ecc1 byte 0 address line15 line14 line13 line12 line11 line10 line9 line8 00000000 r e62b 1 ecc1b1 ecc1 byte 1 address line7 line6 line5 line4 line3 line2 line1 line0 00000000 r e62c 1 ecc1b2 ecc1 byte 2 address col5 col4 col3 col2 col1 col0 line17 line16 00000000 r e62d 1 ecc2b0 ecc2 byte 0 address line15 line14 line13 line12 line11 line10 line9 line8 00000000 r note: 11. read and writes to these registers may require synchronization delay, see technical reference manual for ?synchronization de lay.?
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 30 of 60 e62e 1 ecc2b1 ecc2 byte 1 address line7 line6 line5 line4 line3 line2 line1 line0 00000000 r e62f 1 ecc2b2 ecc2 byte 2 address col5 col4 col3 col2 col1 col0 0 0 00000000 r e630 h.s. 1 ep2fifopfh [11] endpoint 2 / slave fifo programmable flag h decis pktstat in:pkts[2] out:pfc12 in:pkts[1] out:pfc11 in:pkts[0] out:pfc10 0 pfc9 pfc8 10001000 bbbbbrbb e630 f. s . 1 ep2fifopfh [11] endpoint 2 / slave fifo programmable flag h decis pktstat out:pfc12 out:pfc11 out:pfc10 0 pfc9 in:pkts[2] out:pfc8 10001000 bbbbbrbb e631 h.s. 1 ep2fifopfl [11] endpoint 2 / slave fifo programmable flag l pfc7 pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 00000000 rw e631 f. s 1 ep2fifopfl [11] endpoint 2 / slave fifo programmable flag l in:pkts[1] out:pfc7 in:pkts[0] out:pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 00000000 rw e632 h.s. 1 ep4fifopfh [11] endpoint 4 / slave fifo programmable flag h decis pktstat 0 in: pkts[1] out:pfc10 in: pkts[0] out:pfc9 0 0 pfc8 10001000 bbrbbrrb e632 f. s 1 ep4fifopfh [11] endpoint 4 / slave fifo programmable flag h decis pktstat 0 out:pfc10 out:pfc9 0 0 pfc8 10001000 bbrbbrrb e633 h.s. 1 ep4fifopfl [11] endpoint 4 / slave fifo programmable flag l pfc7 pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 00000000 rw e633 f. s 1 ep4fifopfl [11] endpoint 4 / slave fifo programmable flag l in: pkts[1] out:pfc7 in: pkts[0] out:pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 00000000 rw e634 h.s. 1 ep6fifopfh [11] endpoint 6 / slave fifo programmable flag h decis pktstat in:pkts[2] out:pfc12 in:pkts[1] out:pfc11 in:pkts[0] out:pfc10 0 pfc9 pfc8 00001000 bbbbbrbb e634 f. s 1 ep6fifopfh [11] endpoint 6 / slave fifo programmable flag h decis pktstat out:pfc12 out:pfc11 out:pfc10 0 pfc9 in:pkts[2] out:pfc8 00001000 bbbbbrbb e635 h.s. 1 ep6fifopfl [11] endpoint 6 / slave fifo programmable flag l pfc7 pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 00000000 rw e635 f. s 1 ep6fifopfl [11] endpoint 6 / slave fifo programmable flag l in:pkts[1] out:pfc7 in:pkts[0] out:pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 00000000 rw e636 h.s. 1 ep8fifopfh [11] endpoint 8 / slave fifo programmable flag h decis pktstat 0 in: pkts[1] out:pfc10 in: pkts[0] out:pfc9 0 0 pfc8 00001000 bbrbbrrb e636 f. s 1 ep8fifopfh [11] endpoint 8 / slave fifo programmable flag h decis pktstat 0 out:pfc10 out:pfc9 0 0 pfc8 00001000 bbrbbrrb e637 h.s. 1 ep8fifopfl [11] endpoint 8 / slave fifo programmable flag l pfc7 pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 00000000 rw e637 f. s 1 ep8fifopfl [11] endpoint 8 / slave fifo programmable flag l in: pkts[1] out:pfc7 in: pkts[0] out:pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 00000000 rw 8 reserved e640 1 ep2isoinpkts ep2 (if iso) in packets per frame (1-3) aadj 0 0 0 0 0 inppf1 inppf0 00000001 brrrrrbb e641 1 ep4isoinpkts ep4 (if iso) in packets per frame (1-3) aadj 0 0 0 0 0 inppf1 inppf0 00000001 brrrrrrr e642 1 ep6isoinpkts ep6 (if iso) in packets per frame (1-3) aadj 0 0 0 0 0 inppf1 inppf0 00000001 brrrrrbb e643 1 ep8isoinpkts ep8 (if iso) in packets per frame (1-3) aadj 0 0 0 0 0 inppf1 inppf0 00000001 brrrrrrr e644 4 reserved e648 1 inpktend [11] force in packet end skip 0 0 0 ep3 ep2 ep1 ep0 xxxxxxxx w e649 7 outpktend [11] force out packet end skip 0 0 0 ep3 ep2 ep1 ep0 xxxxxxxx w interrupts e650 1 ep2fifoie [11] endpoint 2 slave fifo flag interrupt enable 0 0 0 0 edgepf pf ef ff 00000000 rw e651 1 ep2fifoirq [11,12] endpoint 2 slave fifo flag interrupt request 0 0 0 0 0 pf ef ff 00000000 rrrrrbbb e652 1 ep4fifoie [11] endpoint 4 slave fifo flag interrupt enable 0 0 0 0 edgepf pf ef ff 00000000 rw e653 1 ep4fifoirq [11,12] endpoint 4 slave fifo flag interrupt request 0 0 0 0 0 pf ef ff 00000000 rrrrrbbb e654 1 ep6fifoie [11] endpoint 6 slave fifo flag interrupt enable 0 0 0 0 edgepf pf ef ff 00000000 rw e655 1 ep6fifoirq [11,12] endpoint 6 slave fifo flag interrupt request 0 0 0 0 0 pf ef ff 00000000 rrrrrbbb e656 1 ep8fifoie [11] endpoint 8 slave fifo flag interrupt enable 0 0 0 0 edgepf pf ef ff 00000000 rw e657 1 ep8fifoirq [11,12] endpoint 8 slave fifo flag interrupt request 0 0 0 0 0 pf ef ff 00000000 rrrrrbbb e658 1 ibnie in-bulk-nak interrupt enable 0 0 ep8 ep6 ep4 ep2 ep1 ep0 00000000 rw e659 1 ibnirq [12] in-bulk-nak interrupt request 0 0 ep8 ep6 ep4 ep2 ep1 ep0 00xxxxxx rrbbbbbb e65a 1 nakie endpoint ping-nak / ibn interrupt enable ep8 ep6 ep4 ep2 ep1 ep0 0 ibn 00000000 rw e65b 1 nakirq [12] endpoint ping-nak / ibn interrupt request ep8 ep6 ep4 ep2 ep1 ep0 0 ibn xxxxxx0x bbbbbbrb e65c 1 usbie usb int enables 0 ep0ack hsgrant ures susp sutok sof sudav 00000000 rw e65d 1 usbirq [12] usb interrupt requests 0 ep0ack hsgrant ures susp sutok sof sudav 0xxxxxxx rbbbbbbb e65e 1 epie endpoint interrupt enables ep8 ep6 ep4 ep2 ep1out ep1in ep0out ep0in 00000000 rw e65f 1 epirq [12] endpoint interrupt requests ep8 ep6 ep4 ep2 ep1out ep1in ep0out ep0in 0 rw e660 1 gpifie [11] gpif interrupt enable 0 0 0 0 0 0 gpifwf gpifdone 00000000 rw e661 1 gpifirq [11] gpif interrupt request 0 0 0 0 0 0 gpifwf gpifdone 000000xx rw note: 12. the register can only be reset, it cannot be set. table 5-1. fx2lp register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 31 of 60 e662 1 usberrie usb error interrupt enables isoep8 isoep6 isoep4 isoep2 0 0 0 errlimit 00000000 rw e663 1 usberrirq [12] usb error interrupt requests isoep8 isoep6 isoep4 isoep2 0 0 0 errlimit 0000000x bbbbrrrb e664 1 errcntlim usb error counter and limit ec3 ec2 ec1 ec0 limit3 limit2 limit1 limit0 xxxx0100 rrrrbbbb e665 1 clrerrcnt clear error counter ec3:0 x x x x x x x x xxxxxxxx w e666 1 int2ivec interrupt 2 (usb) autovector 0 i2v4 i2v3 i2v2 i2v1 i2v0 0 0 00000000 r e667 1 int4ivec interrupt 4 (slave fifo & gpif) autovector 1 0 i4v3 i4v2 i4v1 i4v0 0 0 10000000 r e668 1 intset-up interrupt 2&4 set-up 0 0 0 0 av2en 0 int4src av4en 00000000 rw e669 7 reserved input / output e670 1 portacfg i/o porta alternate configuration flagd slcs 0 0 0 0 int1 int0 00000000 rw e671 1 portccfg i/o portc alternate configuration gpifa7 gpifa6 gpifa5 gpifa4 gpifa3 gpifa2 gpifa1 gpifa0 00000000 rw e672 1 portecfg i/o porte alternate configuration gpifa8 t2ex int6 rxd1out rxd0out t2out t1out t0out 00000000 rw e673 4 reserved e677 1 reserved e678 1 i2cs i2c bus control & status start stop lastrd id1 id0 berr ack done 000xx000 bbbrrrrr e679 1 i2dat i2c bus data d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw e67a 1 i2ctl i2c bus control 0 0 0 0 0 0 stopie 400khz 00000000 rw e67b 1 xautodat1 autoptr1 movx access, when aptren=1 d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw e67c 1 xautodat2 autoptr2 movx access, when aptren=1 d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw udma crc e67d 1 udmacrch [11] udma crc msb crc15 crc14 crc13 crc12 crc11 crc10 crc9 crc8 01001010 rw e67e 1 udmacrcl [11] udma crc lsb crc7 crc6 crc5 crc4 crc3 crc2 crc1 crc0 10111010 rw e67f 1 udmacrc- qualifier udma crc qualifier qenable 0 0 0 qstate qsignal2 qsignal1 qsignal0 00000000 brrrbbbb usb control e680 1 usbcs usb control & status hsm 0 0 0 discon nosynsof renum sigrsume x0000000 rrrrbbbb e681 1 suspend put chip into suspend x x x x x x x x xxxxxxxx w e682 1 wakeupcs wakeup control & status wu2 wu wu2pol wupol 0 dpen wu2en wuen xx000101 bbbbrbbb e683 1 togctl to g g l e c o n t r o l q s r io ep3 ep2 ep1 ep0 x0000000 rrrbbbbb e684 1 usbframeh usb frame count h 0 0 0 0 0 fc10 fc9 fc8 00000xxx r e685 1 usbframel usb frame count l fc7 fc6 fc5 fc4 fc3 fc2 fc1 fc0 xxxxxxxx r e686 1 microframe microframe count, 0-7 0 0 0 0 0 mf2 mf1 mf0 00000xxx r e687 1 fnaddr usb function address 0 fa6 fa5 fa4 fa3 fa2 fa1 fa0 0xxxxxxx r e688 2 reserved endpoints e68a 1 ep0bch [11] endpoint 0 byte count h (bc15) (bc14) (bc13) (bc12) (bc11) (bc10) (bc9) (bc8) xxxxxxxx rw e68b 1 ep0bcl [11] endpoint 0 byte count l (bc7) bc6 bc5 bc4 bc3 bc2 bc1 bc0 xxxxxxxx rw e68c 1 reserved e68d 1 ep1outbc endpoint 1 out byte count 0 bc6 bc5 bc4 bc3 bc2 bc1 bc0 0xxxxxxx rw e68e 1 reserved e68f 1 ep1inbc endpoint 1 in byte count 0 bc6 bc5 bc4 bc3 bc2 bc1 bc0 0xxxxxxx rw e690 1 ep2bch [11] endpoint 2 byte count h 0 0 0 0 0 bc10 bc9 bc8 00000xxx rw e691 1 ep2bcl [11] endpoint 2 byte count l bc7/skip bc6 bc5 bc4 bc3 bc2 bc1 bc0 xxxxxxxx rw e692 2 reserved e694 1 ep4bch [11] endpoint 4 byte count h 0 0 0 0 0 0 bc9 bc8 000000xx rw e695 1 ep4bcl [11] endpoint 4 byte count l bc7/skip bc6 bc5 bc4 bc3 bc2 bc1 bc0 xxxxxxxx rw e696 2 reserved e698 1 ep6bch [11] endpoint 6 byte count h 0 0 0 0 0 bc10 bc9 bc8 00000xxx rw e699 1 ep6bcl [11] endpoint 6 byte count l bc7/skip bc6 bc5 bc4 bc3 bc2 bc1 bc0 xxxxxxxx rw e69a 2 reserved e69c 1 ep8bch [11] endpoint 8 byte count h 0 0 0 0 0 0 bc9 bc8 000000xx rw e69d 1 ep8bcl [11] endpoint 8 byte count l bc7/skip bc6 bc5 bc4 bc3 bc2 bc1 bc0 xxxxxxxx rw e69e 2 reserved e6a0 1 ep0cs endpoint 0 control and status hsnak 0 0 0 0 0 busy stall 10000000 bbbbbbrb e6a1 1 ep1outcs endpoint 1 out control and status 0 0 0 0 0 0 busy stall 00000000 bbbbbbrb e6a2 1 ep1incs endpoint 1 in control and status 0 0 0 0 0 0 busy stall 00000000 bbbbbbrb e6a3 1 ep2cs endpoint 2 control and status 0 npak2 npak1 npak0 full empty 0 stall 00101000 rrrrrrrb table 5-1. fx2lp register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 32 of 60 e6a4 1 ep4cs endpoint 4 control and status 0 0 npak1 npak0 full empty 0 stall 00101000 rrrrrrrb e6a5 1 ep6cs endpoint 6 control and status 0 npak2 npak1 npak0 full empty 0 stall 00000100 rrrrrrrb e6a6 1 ep8cs endpoint 8 control and status 0 0 npak1 npak0 full empty 0 stall 00000100 rrrrrrrb e6a7 1 ep2fifoflgs endpoint 2 slave fifo flags 0 0 0 0 0 pf ef ff 00000010 r e6a8 1 ep4fifoflgs endpoint 4 slave fifo flags 0 0 0 0 0 pf ef ff 00000010 r e6a9 1 ep6fifoflgs endpoint 6 slave fifo flags 0 0 0 0 0 pf ef ff 00000110 r e6aa 1 ep8fifoflgs endpoint 8 slave fifo flags 0 0 0 0 0 pf ef ff 00000110 r e6ab 1 ep2fifobch endpoint 2 slave fifo total byte count h 0 0 0 bc12 bc11 bc10 bc9 bc8 00000000 r e6ac 1 ep2fifobcl endpoint 2 slave fifo total byte count l bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 00000000 r e6ad 1 ep4fifobch endpoint 4 slave fifo total byte count h 0 0 0 0 0 bc10 bc9 bc8 00000000 r e6ae 1 ep4fifobcl endpoint 4 slave fifo total byte count l bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 00000000 r e6af 1 ep6fifobch endpoint 6 slave fifo total byte count h 0 0 0 0 bc11 bc10 bc9 bc8 00000000 r e6b0 1 ep6fifobcl endpoint 6 slave fifo total byte count l bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 00000000 r e6b1 1 ep8fifobch endpoint 8 slave fifo total byte count h 0 0 0 0 0 bc10 bc9 bc8 00000000 r e6b2 1 ep8fifobcl endpoint 8 slave fifo total byte count l bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 00000000 r e6b3 1 sudptrh set-up data pointer high address byte a15 a14 a13 a12 a11 a10 a9 a8 xxxxxxxx rw e6b4 1 sudptrl set-up data pointer low address byte a7 a6 a5 a4 a3 a2 a1 0 xxxxxxx0 bbbbbbbr e6b5 1 sudptrctl set-up data pointer auto mode 0 0 0 0 0 0 0 sdpauto 00000001 rw 2 reserved e6b8 8 set-updat 8 bytes of set-up data d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx r set-updat[0] = bmrequesttype set-updat[1] = bmrequest set-updat[2:3] = wval- ue set-updat[4:5] = wind- ex set-updat[6:7] = wlength gpif e6c0 1 gpifwfselect waveform selector singlewr1 singlewr0 singlerd1 singlerd0 fifowr1 fifowr0 fiford1 fiford0 11100100 rw e6c1 1 gpifidlecs gpif done, gpif idle drive mode done 0 0 0 0 0 0 idledrv 10000000 rw e6c2 1 gpifidlectl inactive bus, ctl states 0 0 ctl5 ctl4 ctl3 ctl2 ctl1 ctl0 11111111 rw e6c3 1 gpifctlcfg ctl drive type trictl 0 ctl5 ctl4 ctl3 ctl2 ctl1 ctl0 00000000 rw e6c4 1 gpifadrh [11] gpif address h 0 0 0 0 0 0 0 gpifa8 00000000 rw e6c5 1 gpifadrl [11] gpif address l gpifa7 gpifa6 gpifa5 gpifa4 gpifa3 gpifa2 gpifa1 gpifa0 00000000 rw flowstate e6c6 1 flowstate flowstate enable and selector fse 0 0 0 0 fs2 fs1 fs0 00000000 brrrrbbb e6c7 1 flowlogic flowstate logic lfunc1 lfunc0 terma2 terma1 terma0 termb2 termb1 termb0 00000000 rw e6c8 1 floweq0ctl ctl-pin states in flowstate (when logic = 0) ctl0e3 ctl0e2 ctl0e1/ ctl5 ctl0e0/ ctl4 ctl3 ctl2 ctl1 ctl0 00000000 rw e6c9 1 floweq1ctl ctl-pin states in flow- state (when logic = 1) ctl0e3 ctl0e2 ctl0e1/ ctl5 ctl0e0/ ctl4 ctl3 ctl2 ctl1 ctl0 00000000 rw e6ca 1 flowholdoff holdoff configuration hoperiod3 hoperiod2 hoperiod1 hoperiod 0 hostate hoctl2 hoctl1 hoctl0 00010010 rw e6cb 1 flowstb flowstate strobe configuration slave rdyasync ctltogl sustain 0 mstb2 mstb1 mstb0 00100000 rw e6cc 1 flowstbedge flowstate rising/falling edge configuration 0 0 0 0 0 0 falling rising 00000001 rrrrrrbb e6cd 1 flowstbperiod master-strobe half-period d7 d6 d5 d4 d3 d2 d1 d0 00000010 rw e6ce 1 gpiftcb3 [11] gpif transaction count byte 3 tc31 tc30 tc29 tc28 tc27 tc26 tc25 tc24 00000000 rw e6cf 1 gpiftcb2 [11] gpif transaction count byte 2 tc23 tc22 tc21 tc20 tc19 tc18 tc17 tc16 00000000 rw e6d0 1 gpiftcb1 [11] gpif transaction count byte 1 tc15 tc14 tc13 tc12 tc11 tc10 tc9 tc8 00000000 rw e6d1 1 gpiftcb0 [11] gpif transaction count byte 0 tc7 tc6 tc5 tc4 tc3 tc2 tc1 tc0 00000001 rw 2 reserved 00000000 rw table 5-1. fx2lp register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 33 of 60 reserved reserved e6d2 1 ep2gpifflgsel [11] endpoint 2 gpif flag select 0 0 0 0 0 0 fs1 fs0 00000000 rw e6d3 1 ep2gpifpfstop endpoint 2 gpif stop transaction on prog. flag 0 0 0 0 0 0 0 fifo2flag 00000000 rw e6d4 1 ep2gpiftrig [11] endpoint 2 gpif trigger x x x x x x x x xxxxxxxx w 3 reserved reserved reserved e6da 1 ep4gpifflgsel [11] endpoint 4 gpif flag select 0 0 0 0 0 0 fs1 fs0 00000000 rw e6db 1 ep4gpifpfstop endpoint 4 gpif stop transaction on gpif flag 0 0 0 0 0 0 0 fifo4flag 00000000 rw e6dc 1 ep4gpiftrig [11] endpoint 4 gpif trigger x x x x x x x x xxxxxxxx w 3 reserved reserved reserved e6e2 1 ep6gpifflgsel [11] endpoint 6 gpif flag select 0 0 0 0 0 0 fs1 fs0 00000000 rw e6e3 1 ep6gpifpfstop endpoint 6 gpif stop transaction on prog. flag 0 0 0 0 0 0 0 fifo6flag 00000000 rw e6e4 1 ep6gpiftrig [11] endpoint 6 gpif trigger x x x x x x x x xxxxxxxx w 3 reserved reserved reserved e6ea 1 ep8gpifflgsel [11] endpoint 8 gpif flag select 0 0 0 0 0 0 fs1 fs0 00000000 rw e6eb 1 ep8gpifpfstop endpoint 8 gpif stop transaction on prog. flag 0 0 0 0 0 0 0 fifo8flag 00000000 rw e6ec 1 ep8gpiftrig [11] endpoint 8 gpif trigger x x x x x x x x xxxxxxxx w 3 reserved e6f0 1 xgpifsgldath gpif data h (16-bit mode only) d15 d14 d13 d12 d11 d10 d9 d8 xxxxxxxx rw e6f1 1 xgpifsgldatlx read/write gpif data l & trigger transaction d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw e6f2 1 xgpifsgldatl- nox read gpif data l, no transaction trigger d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx r e6f3 1 gpifreadycfg internal rdy, sync/async, rdy pin states intrdy sas tcxrdy5 0 0 0 0 0 00000000 bbbrrrrr e6f4 1 gpifreadystat gpif ready status 0 0 rdy5 rdy4 rdy3 rdy2 rdy1 rdy0 00xxxxxx r e6f5 1 gpifabort abort gpif waveforms x x x x x x x x xxxxxxxx w e6f6 2 reserved endpoint buffers e740 64 ep0buf ep0-in/-out buffer d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw e780 64 ep10utbuf ep1-out buffer d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw e7c0 64 ep1inbuf ep1-in buffer d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw e800 2048 reserved rw f000 1024 ep2fifobuf 512/1024-byte ep 2 / slave fifo buffer (in or out) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw f400 512 ep4fifobuf 512 byte ep 4 / slave fifo buffer (in or out) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw f600 512 reserved f800 1024 ep6fifobuf 512/1024-byte ep 6 / slave fifo buffer (in or out) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw fc00 512 ep8fifobuf 512 byte ep 8 / slave fifo buffer (in or out) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw fe00 512 reserved xxxx i2c configuration byte 0 discon 0 0 0 0 0 400khz xxxxxxxx [14] n/a special function registers (sfrs) 80 1 ioa [13] port a (bit addressable) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw 81 1 sp stack pointer d7 d6 d5 d4 d3 d2 d1 d0 00000111 rw 82 1 dpl0 data pointer 0 l a7 a6 a5 a4 a3 a2 a1 a0 00000000 rw 83 1 dph0 data pointer 0 h a15 a14 a13 a12 a11 a10 a9 a8 00000000 rw 84 1 dpl1 [13] data pointer 1 l a7 a6 a5 a4 a3 a2 a1 a0 00000000 rw 85 1 dph1 [13] data pointer 1 h a15 a14 a13 a12 a11 a10 a9 a8 00000000 rw 86 1 dps [13] data pointer 0/1 select 0 0 0 0 0 0 0 sel 00000000 rw 87 1 pcon power control smod0 x 1 1 x x x idle 00110000 rw notes: 13. sfrs not part of the standard 8051 architecture. 14. if no eeprom is detected by the sie then the default is 00000000. table 5-1. fx2lp register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 34 of 60 88 1 tcon timer/counter control (bit addressable) tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00000000 rw 89 1 tmod timer/counter mode control gate ct m1 m0 gate ct m1 m0 00000000 rw 8a 1 tl0 timer 0 reload l d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw 8b 1 tl1 timer 1 reload l d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw 8c 1 th0 timer 0 reload h d15 d14 d13 d12 d11 d10 d9 d8 00000000 rw 8d 1 th1 timer 1 reload h d15 d14 d13 d12 d11 d10 d9 d8 00000000 rw 8e 1 ckcon [13] clock control x x t2m t1m t0m md2 md1 md0 00000001 rw 8f 1 reserved 90 1 iob [13] port b (bit addressable) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw 91 1 exif [13] external interrupt flag(s) ie5 ie4 i2cint usbnt 1 0 0 0 00001000 rw 92 1 mpage [13] upper addr byte of movx using @r0 / @r1 a15 a14 a13 a12 a11 a10 a9 a8 00000000 rw 93 5 reserved 98 1 scon0 serial port 0 control (bit addressable) sm0_0 sm1_0 sm2_0 ren_0 tb8_0 rb8_0 ti_0 ri_0 00000000 rw 99 1 sbuf0 serial port 0 data buffer d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw 9a 1 autoptrh1 [13] autopointer 1 address h a15 a14 a13 a12 a11 a10 a9 a8 00000000 rw 9b 1 autoptrl1 [13] autopointer 1 address l a7 a6 a5 a4 a3 a2 a1 a0 00000000 rw 9c 1 reserved 9d 1 autoptrh2 [13] autopointer 2 address h a15 a14 a13 a12 a11 a10 a9 a8 00000000 rw 9e 1 autoptrl2 [13] autopointer 2 address l a7 a6 a5 a4 a3 a2 a1 a0 00000000 rw 9f 1 reserved a0 1 ioc [13] port c (bit addressable) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw a1 1 int2clr [13] interrupt 2 clear x x x x x x x x xxxxxxxx w a2 1 int4clr [13] interrupt 4 clear x x x x x x x x xxxxxxxx w a3 5 reserved a8 1 ie interrupt enable (bit addressable) ea es1 et2 es0 et1 ex1 et0 ex0 00000000 rw a9 1 reserved aa 1 ep2468stat [13] endpoint 2,4,6,8 status flags ep8f ep8e ep6f ep6e ep4f ep4e ep2f ep2e 01011010 r ab 1 ep24fifoflgs [13] endpoint 2,4 slave fifo status flags 0 ep4pf ep4ef ep4ff 0 ep2pf ep2ef ep2ff 00100010 r ac 1 ep68fifoflgs [13] endpoint 6,8 slave fifo status flags 0 ep8pf ep8ef ep8ff 0 ep6pf ep6ef ep6ff 01100110 r ad 2 reserved af 1 autoptrsetup [13] autopointer 1&2 set-up 0 0 0 0 0 aptr2inc aptr1inc aptren 00000110 rw b0 1 iod [13] port d (bit addressable) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw b1 1 ioe [13] port e (not bit addressable) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw b2 1 oea [13] port a output enable d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw b3 1 oeb [13] port b output enable d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw b4 1 oec [13] port c output enable d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw b5 1 oed [13] port d output enable d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw b6 1 oee [13] port e output enable d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw b7 1 reserved b8 1 ip interrupt priority (bit ad- dressable) 1 ps1 pt2 ps0 pt1 px1 pt0 px0 10000000 rw b9 1 reserved ba 1 ep01stat [13] endpoint 0&1 status 0 0 0 0 0 ep1inbsy ep1outbs y ep0bsy 00000000 r bb 1 gpiftrig [13, 11] endpoint 2,4,6,8 gpif slave fifo trigger done 0 0 0 0 rw ep1 ep0 10000xxx brrrrbbb bc 1 reserved bd 1 gpifsgldath [13] gpif data h (16-bit mode only) d15 d14 d13 d12 d11 d10 d9 d8 xxxxxxxx rw be 1 gpifsgldatlx [13] gpif data l w/ trigger d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw bf 1 gpifsgldatl- nox [13] gpif data l w/ no trigger d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx r c0 1 scon1 [13] serial port 1 control (bit addressable) sm0_1 sm1_1 sm2_1 ren_1 tb8_1 rb8_1 ti_1 ri_1 00000000 rw c1 1 sbuf1 [13] serial port 1 data buffer d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw c2 6 reserved c8 1 t2con timer/counter 2 control (bit addressable) tf2 exf2 rclk tclk exen2 tr2 ct2 cprl2 00000000 rw c9 1 reserved ca 1 rcap2l capture for timer 2, au- to-reload, up-counter d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw cb 1 rcap2h capture for timer 2, au- to-reload, up-counter d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw cc 1 tl2 timer 2 reload l d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw cd 1 th2 timer 2 reload h d15 d14 d13 d12 d11 d10 d9 d8 00000000 rw ce 2 reserved table 5-1. fx2lp register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 35 of 60 d0 1 psw program status word (bit addressable) cy ac f0 rs1 rs0 ov f1 p 00000000 rw d1 7 reserved d8 1 eicon [13] external interrupt control smod1 1 eresi resi int6 0 0 0 01000000 rw d9 7 reserved e0 1 acc accumulator (bit address- able) d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw e1 7 reserved e8 1 eie [13] external interrupt en- able(s) 1 1 1 ex6 ex5 ex4 ei2c eusb 11100000 rw e9 7 reserved f0 1 b b (bit addressable) d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw f1 7 reserved f8 1 eip [13] external interrupt priority control 1 1 1 px6 px5 px4 pi2c pusb 11100000 rw f9 7 reserved table 5-1. fx2lp register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access r = read-only bit w = write-only bit b = both read/write bit r = all bits read-only w = all bits write-only
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 36 of 60 6.0 absolute maximum ratings storage temperature ............................................................................................................ ...............................?65c to +150c ambient temperature with power supplied (commercial) ........................................................................... .............0c to +70c ambient temperature with power supplied (industrial) ........................................................................... ............?40c to +105c supply voltage to ground potential . .............. .............. .............. .............. .............. ........... ........... ........................... ?0.5v to +4.0v dc input voltage to any input pin .............................................................................................. ......................................5.25v [15] dc voltage applied to outputs in high z state.................................................................................. ........... ?0.5v to vcc + 0.5v power dissipation ...................... ........................................................................................ ............. .............. .............. ...... 300 mw static discharge voltage ....................................................................................................... ............................................ > 2000v max output current, per i/o port ............................................................................................... .......................................... 10 ma max output current, all five i/o ports (128- and 100-pin packages)............................................................. ....................... 50 ma 7.0 operating conditions t a (ambient temperature under bias) commercial ................................................................................... .............. 0c to +70c t a (ambient temperature under bias) industrial ............ ....................................................................... ..............?40c to +105c supply voltage ................................................................................................................. ................................... +3.00v to +3.60v ground voltage ................................................................................................................. ......................................................... 0v f osc (oscillator or crystal frequency) .............................................................................. 24 mhz 100 ppm , parallel resonant 8.0 thermal characteristics the following table displays the thermal characteristics of various packages the junction temperature j, can be calculated using the following equation j = p* ja + a where, p = power ja = junction to ambient temperature ( jc + ca ) a = ambient temperature (70 c) the case temperature c, can be calculated using the following equation c = p* ca + a where, p = power ca = case to ambient temperature a = ambient temperature (70 c) notes: 15. it is recommended to not power i/o with chip power off. table 8-1. thermal characteristics package a ambient temperature (c) jc junction to case temperature (c/w) ca case to ambient temperature (c/w) ja junction to ambient temperature jc + ca (c/w) 56 ssop 70 24.4 23.3 47.7 100 tqfp 70 11.9 34.0 45.9 128 tqfp 70 15.5 27.7 43.2 56 qfn 70 10.6 14.6 25.2 56 vfbga 70 30.9 27.7 58.6
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 37 of 60 9.0 dc characteristics notes: 16. measured at max vcc, 25c. 9.1 usb transceiver usb 2.0-compliant in full- and high-speed modes. 10.0 ac electrical characteristics 10.1 usb transceiver usb 2.0-compliant in full- and high-speed modes. table 9-1. dc characteristics parameter description conditions min. typ. max. unit vcc supply voltage 3.00 3.3 3.60 v vcc ramp up 0 to 3.3v 200 s v ih input high voltage 2 5.25 v v il input low voltage ?0.5 0.8 v v ih_x crystal input high voltage 2 5.25 v v il_x crystal input low voltage ?0.5 0.8 v i i input leakage current 0< v in < vcc 10 a v oh output voltage high i out = 4 ma 2.4 v v ol output low voltage i out = ?4 ma 0.4 v i oh output current high 4ma i ol output current low 4ma c in input pin capacitance except d+/d? 10 pf d+/d? 15 pf i susp suspend current connected 300 380 [16] a cy7c68014/cy7c68016 disconnected 100 150 [16] a suspend current connected 0.5 1.2 [16] m a cy7c68013/cy7c68015 disconnected 0.3 1.0 [16] m a i cc supply current 8051 running, connected to usb hs 50 85 ma 8051 running, connected to usb fs 35 65 ma t reset reset time after valid power vcc min = 3.0v 5.0 ms pin reset after powered on 200 s
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 38 of 60 10.2 program memory read notes: 17. clkout is shown with positive polarity. 18. t acc1 is computed from the above parameters as follows: t acc1 (24 mhz) = 3*t cl ? t av ? t dsu = 106 ns t acc1 (48 mhz) = 3*t cl ? t av ? t dsu = 43 ns. t cl t dh t soel t scsl psen# d[7..0] oe# a[15..0] cs# t stbl data in t acc1 t av t stbh t av figure 10-1. program memo ry read timing diagram clkout [17] [18] table 10-1. program memory read parameters parameter description mi n. typ. max. unit notes t cl 1/clkout frequency 20.83 ns 48 mhz 41.66 ns 24 mhz 83.2 ns 12 mhz t av delay from clock to valid address 0 10.7 ns t stbl clock to psen low 0 8 ns t stbh clock to psen high 0 8 ns t soel clock to oe low 11.1 ns t scsl clock to cs low 13 ns t dsu data set-up to clock 9.6 ns t dh data hold time 0 ns
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 39 of 60 10.3 data memory read data in t cl a[15..0] t av t av rd# t stbl t stbh t dh d[7..0] data in t acc1 [19 t dsu stretch = 0 stretch = 1 t cl a[15..0] t av rd# t dh d[7..0] t acc1 [19] t dsu cs# cs# t scsl oe# t soel figure 10-2. data memory read timing diagram clkout [17] clkout [17] table 10-2. data memory read parameters parameter description mi n. typ. max. unit notes t cl 1/clkout frequency 20.83 ns 48 mhz 41.66 ns 24 mhz 83.2 ns 12 mhz t av delay from clock to valid address 10.7 ns t stbl clock to rd low 11 ns t stbh clock to rd high 11 ns t scsl clock to cs low 13 ns t soel clock to oe low 11.1 ns t dsu data set-up to clock 9.6 ns t dh data hold time 0 ns when using the autpoptr1 or autoptr2 to address external memory, the address of autoptr1 will only be active while either rd# or wr# are active. the address of autoptr2 will be active throughout the cycle a nd meet the above address valid time for which is based on the stretch value note: 19. t acc2 and t acc3 are computed from the above parameters as follows: t acc2 (24 mhz) = 3*t cl ? t av ?t dsu = 106 ns t acc2 (48 mhz) = 3*t cl ? t av ? t dsu = 43 ns t acc3 (24 mhz) = 5*t cl ? t av ?t dsu = 190 ns t acc3 (48 mhz) = 5*t cl ? t av ? t dsu = 86 ns.
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 40 of 60 10.4 data memory write when using the autpoptr1 or autoptr2 to address external memory, the address of autoptr1 will only be active while either rd# or wr# are active. the address of autoptr2 will be active throughout the cycle and meet the above address valid time for which is based on the stretch value. t off1 clkout a[15..0] wr# t av d[7..0] t cl t stbl t stbh data out t off1 clkout a[15..0] wr# t av d[7..0] t cl data out stretch = 1 t on1 t scsl t av cs# t on1 cs# figure 10-3. data memory write timing diagram table 10-3. data memory write parameters parameter description min. max. unit notes t av delay from clock to valid address 0 10.7 ns t stbl clock to wr pulse low 0 11.2 ns t stbh clock to wr pulse high 0 11.2 ns t scsl clock to cs pulse low 13.0 ns t on1 clock to data turn-on 0 13.1 ns t off1 clock to data hold time 0 13.1 ns
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 41 of 60 10.5 portc strobe feature timings the rd# and wr# are present in the 100-pin version and the 128-pin package. in these 100-pin and 128-pin versions, an 8051 control bit can be set to pulse the rd# and wr# pins when the 8051 reads from/writes to portc. this feature is enabled by setting portcstb bit in cpucs register. the rd# and wr# strobes are asserted for two clkout cycles when portc is accessed. the wr# strobe will be asse rted two clock cycles after portc is updated and will be active for two clock cycles after that as shown in figure 10-4 . as for read, the value of port c three clock cycles before the assertion of rd# is the value that the 8051 reads in. the rd# is pulsed for 2 clock cycles after 3 clock cycles from the point when the 8051 has performed a read function on portc. the way the feature is intended to work is that the rd# signal will prompt the external logic to prepare the next data byte. nothing gets sampled internally on assertion of the rd# signal itself. it is just a ?prefetch? type signal to get the next data byte prepared. so, using it with that in mind should easily meet the set-up time to the next read. the purpose of this pulsing of rd# is to let the external peripheral know that the 8051 is done reading portc and the data was latched into portc three clkout cycles prior to asserting the rd# signal. once the rd# is pulsed the external logic may update the data on portc. following is the timing diagram of the read and write strobing function on accessing portc. refer to section 10.3 and section 10.4 for details on propagation delay of rd# and wr# signals. clkout wr# t clkout portc is updated figure 10-4. wr# strobe function when portc is accessed by 8051 t stbl t stbh clkout t clkout data must be held for 3 clk cylces data can be updated by external logic 8051 reads portc rd# figure 10-5. rd# strobe function when portc is accessed by 8051 t stbl t stbh
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 42 of 60 10.6 gpif synchronous signals data(output) t xgd ifclk rdy x data(input) valid t sry t ryh t ifclk t sgd ctl x t xctl t dah n n+1 gpifadr[8:0] t sga figure 10-6. gpif synchronous signals timing diagram [20] table 10-4. gpif synchronous signals pa rameters with internally sourced ifclk [20, 21] parameter description min. max. unit t ifclk ifclk period 20.83 ns t sry rdy x to clock set-up time 8.9 ns t ryh clock to rdy x 0ns t sgd gpif data to clock set-up time 9.2 ns t dah gpif data hold time 0 ns t sga clock to gpif address propagation delay 7.5 ns t xgd clock to gpif data output propagation delay 11 ns t xctl clock to ctl x output propagation delay 6.7 ns table 10-5. gpif synchronous signals parameters with externally sourced ifclk [21] parameter description min. max. unit t ifclk ifclk period [22] 20.83 200 ns t sry rdy x to clock set-up time 2.9 ns t ryh clock to rdy x 3.7 ns t sgd gpif data to clock set-up time 3.2 ns t dah gpif data hold time 4.5 ns t sga clock to gpif address propagation delay 11.5 ns t xgd clock to gpif data output propagation delay 15 ns t xctl clock to ctl x output propagation delay 10.7 ns notes: 20. dashed lines denote signals with programmable polarity. 21. gpif asynchronous rdy x signals have a minimum set-up time of 50 ns when using internal 48-mhz ifclk. 22. ifclk must not exceed 48 mhz.
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 43 of 60 10.7 slave fifo synchronous read ifclk slrd flags sloe t srd t rdh t oeon t xfd t xflg data t ifclk n+1 t oeoff n figure 10-7. slave fifo sync hronous read timing diagram [20] table 10-6. slave fifo synchronous read parameters with internally sourced ifclk [21] parameter description min. max. unit t ifclk ifclk period 20.83 ns t srd slrd to clock set-up time 18.7 ns t rdh clock to slrd hold time 0 ns t oeon sloe turn-on to fifo data valid 10.5 ns t oeoff sloe turn-off to fifo data hold 10.5 ns t xflg clock to flags output propagation delay 9.5 ns t xfd clock to fifo data output propagation delay 11 ns table 10-7. slave fifo synchronous read parameters with externally sourced ifclk [21] parameter description min. max. unit t ifclk ifclk period 20.83 200 ns t srd slrd to clock set-up time 12.7 ns t rdh clock to slrd hold time 3.7 ns t oeon sloe turn-on to fifo data valid 10.5 ns t oeoff sloe turn-off to fifo data hold 10.5 ns t xflg clock to flags output propagation delay 13.5 ns t xfd clock to fifo data output propagation delay 15 ns
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 44 of 60 10.8 slave fifo asynchronous read slrd flags t rdpwl t rdpwh sloe t xflg t xfd data t oeon t oeoff n+1 n figure 10-8. slave fifo asynchronous read timing diagram [20] table 10-8. slave fifo asynchronous read parameters [23] parameter description min. max. unit t rdpwl slrd pulse width low 50 ns t rdpwh slrd pulse width high 50 ns t xflg slrd to flags output propagation delay 70 ns t xfd slrd to fifo data output propagation delay 15 ns t oeon sloe turn-on to fifo data valid 10.5 ns t oeoff sloe turn-off to fifo data hold 10.5 ns note: 23. slave fifo asynchronous parameter val ues use internal ifclk setting at 48 mhz.
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 45 of 60 10.9 slave fifo synchronous write z z t sfd t fdh data ifclk slwr flags t wrh t xflg t ifclk t swr n figure 10-9. slave fifo synchronous write timing diagram [20] table 10-9. slave fifo synchronous write parameters with internally sourced ifclk [21] parameter description min. max. unit t ifclk ifclk period 20.83 ns t swr slwr to clock set-up time 18.1 ns t wrh clock to slwr hold time 0 ns t sfd fifo data to clock set-up time 9.2 ns t fdh clock to fifo data hold time 0 ns t xflg clock to flags output propagation time 9.5 ns table 10-10. slave fifo synchronous write parameters with externally sourced ifclk [21] parameter description min. max. unit t ifclk ifclk period 20.83 200 ns t swr slwr to clock set-up time 12.1 ns t wrh clock to slwr hold time 3.6 ns t sfd fifo data to clock set-up time 3.2 ns t fdh clock to fifo data hold time 4.5 ns t xflg clock to flags output propagation time 13.5 ns
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 46 of 60 10.10 slave fifo asynchronous write 10.11 slave fifo synchronous packet end strobe there is no specific timing requirement that needs to be met for asserting pktend pin with regards to asserting slwr. pktend can be asserted with the last data value clocked into the fifos or thereafter. the only consideration is the set-up time t spe and the hold time t peh must be met. although there are no specific timing requirements for the pktend assertion, there is a sp ecific corner case condition that needs attention while usin g the pktend to commit a one byte/word packet. there is an additional timing requirement that need to be met when the fifo is configured to operate in data t sfd t fdh flags t xfd slwr/slcs# t wrpwh t wrpwl figure 10-10. slave fifo asyn chronous write timing diagram [20] slwr table 10-11. slave fifo asynchronous write parameters with internally sourced ifclk [23] parameter description min. max. unit t wrpwl slwr pulse low 50 ns t wrpwh slwr pulse high 70 ns t sfd slwr to fifo data set-up time 10 ns t fdh fifo data to slwr hold time 10 ns t xfd slwr to flags output propagation delay 70 ns flags t xflg ifclk pktend t spe t peh figure 10-11. slave fifo synchronous packet end strobe timing diagram [20] table 10-12. slave fifo synchronous packet end strobe parameters with internally sourced ifclk [21] parameter description min. max. unit t ifclk ifclk period 20.83 ns t spe pktend to clock set-up time 14.6 ns t peh clock to pktend hold time 0 ns t xflg clock to flags output propagation delay 9.5 ns table 10-13. slave fifo synchronous packet end strobe parameters with externally sourced ifclk [21] parameter description min. max. unit t ifclk ifclk period 20.83 200 ns t spe pktend to clock set-up time 8.6 ns t peh clock to pktend hold time 2.5 ns t xflg clock to flags output propagation delay 13.5 ns
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 47 of 60 auto mode and it is desired to send two packets back to back: a full packet (full defined as the number of bytes in the fifo meeting the level set in autoinlen register) committed automatically followed by a short one byte/word packet committed manually using the pktend pin. in this particular scenario, user must make sure to assert pktend at least one clock cycle after the rising edge t hat caused the last byte/word to be clocked into the previous auto committed packet. figure 10-12 below shows this scenario. x is the value the autoinlen register is set to when the in endpoint is configured to be in auto mode. figure 10-12 shows a scenario where two packets are being committed. the first packet gets committed automatically when the number of bytes in the fifo reaches x (value set in autoinlen register) and the second one byte/word short packet being committed manually using pktend. note that there is at least one ifclk cycl e timing between the assertion of pktend and clocking of the last byte of the previous packet (causing the packet to be commi tted automatically). failing to adhere to this timing, will result in the fx2 failing to send the one byte/word short packet. 10.12 slave fifo asynchronous packet end strobe table 10-14. slave fifo asynchronous packet end strobe parameters [23] parameter description min. max. unit t pepwl pktend pulse width low 50 ns t pwpwh pktend pulse width high 50 ns t xflg pktend to flags output propagation delay 115 ns ifclk slwr data figure 10-12. slave fifo synchronou s write sequence and timing diagram [20] t ifclk >= t swr >= t wrh x-2 pktend x-3 t fah t spe t peh fifoadr t sfd t sfd t sfd x-4 t fdh t fdh t fdh t sfa 1 x t sfd t sfd t sfd x-1 t fdh t fdh t fdh at least one ifclk cycle flags t xflg pktend t pepwl t pepwh figure 10-13. slave fifo asynchronous packet end strobe timing diagram [20]
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 48 of 60 10.13 slave fifo output enable 10.14 slave fifo address to flags/data table 10-15. slave fifo output enable parameters parameter description min. max. unit t oeon sloe assert to fifo data output 10.5 ns t oeoff sloe deassert to fifo data hold 10.5 ns table 10-16. slave fifo address to flags/data parameters parameter description min. max. unit t xflg fifoadr[1:0] to flags outp ut propagation delay 10.7 ns t xfd fifoadr[1:0] to fifodata ou tput propagation delay 14.3 ns sloe data t oeon t oeoff figure 10-14. slave fifo output enable timing diagram [20] fifoadr [1.0] data t xflg t xfd flags nn+1 figure 10-15. slave fifo address to flags/data timing diagram [20]
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 49 of 60 10.15 slave fifo synchronous address 10.16 slave fifo asynchronous address table 10-17. slave fifo synchronous address parameters [21] parameter description min. max. unit t ifclk interface clock period 20.83 200 ns t sfa fifoadr[1:0] to clock set-up time 25 ns t fah clock to fifoadr[1:0] hold time 10 ns slave fifo asynchronous address parameters [23] parameter description min. max. unit t sfa fifoadr[1:0] to slrd/slwr /pktend set-up time 10 ns t fah rd/wr/pktend to fifoa dr[1:0] hold time 10 ns ifclk slcs/fifoadr [1:0] t sfa t fah figure 10-16. slave fifo synchronous address timing diagram [20] slrd/slwr/pktend slcs/fifoadr [1:0] t sfa t fah figure 10-17. slave fifo asynchronous address timing diagram [20]
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 50 of 60 10.17 sequence diagram 10.17.1 single and burst synchronous read example figure 10-18 shows the timing relationship of the slave fifo signals during a synchronous fifo read using ifclk as the synchronizing clock. the diagram illustrates a single read followed by a burst read. ? at t = 0 the fifo address is stable and the signal slcs is asserted (slcs may be tied low in some applications). note: t sfa has a minimum of 25 ns. this means when ifclk is running at 48 mhz, the fifo address set-up time is more than one ifclk cycle. ? at t = 1, sloe is asserted. sloe is an output enable only, whose sole function is to drive the data bus. the data that is driven on the bus is the data that the internal fifo pointer is currently pointing to. in this example it is the first data value in the fifo. note: the data is pre-fetched and is driven on the bus when sloe is asserted. ? at t = 2, slrd is asserted. sl rd must meet the set-up time of t srd (time from asserting the slrd signal to the rising edge of the ifclk) and maintain a minimum hold time of t rdh (time from the ifclk edge to the deassertion of the slrd signal). if the slcs signal is used, it must be asserted before slrd is asserted (i.e., the slcs and slrd signals must both be asserted to start a valid read condition). ? the fifo pointer is updated on the rising edge of the ifclk, while slrd is asserted. this st arts the propagation of data from the newly addressed location to the data bus. after a propagation delay of t xfd (measured from the rising edge of ifclk) the new data value is present. n is the first data value read from the fifo. in order to have data on the fifo data bus, sloe must also be asserted. the same sequence of events are shown for a burst read and are marked with the time indicators of t = 0 through 5. note: for the burst mode, the slrd and sloe are left asserted during the entire duration of the read. in the burst read mode, when sloe is asserted, data indexed by the fifo pointer is on the data bus. during the firs t read cycle, on the rising edge of the clock the fifo pointer is updated and increments to point to address n+1. for each subsequent rising edge of ifclk, while the slrd is assert ed, the fifo pointer is incre- mented and the next data value is placed on the data bus. ifclk slrd flags sloe data figure 10-18. slave fifo synchronous read sequence and timing diagram [20] t srd t rdh t oeon t xfd t xflg t ifclk n+1 data driven: n >= t srd t oeon t xfd n+2 t xfd t xfd >= t rdh t oeoff n+4 n+3 t oeoff t sfa t fah fifoadr slcs t=0 n+1 t=1 t=2 t=3 t=4 t fah t=0 t sfa t=1 t=2 t=3 t=4 nn n+1 n+2 fifo pointer n+3 fifo data bus n+4 not driven driven: n sloe slrd n+1 n+2 n+3 not driven slrd sloe ifclk figure 10-19. slave fifo synchronous sequence of events diagram ifclk ifclk ifclk ifclk n+4 n+4 ifclk ifclk ifclk ifclk slrd n+1 slrd n+1 n+1 sloe not driven n+4 n+4 ifclk sloe
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 51 of 60 10.17.2 single and burs t synchronous write the figure 10-20 shows the timing relationship of the slave fifo signals during a synchronous write using ifclk as the synchronizing clock. the diag ram illustrates a single write followed by burst write of 3 bytes and committing all 4 bytes as a short packet using the pktend pin. ? at t = 0 the fifo address is stable and the signal slcs is asserted. (slcs may be tied low in some applications) note: t sfa has a minimum of 25 ns. this means when ifclk is running at 48 mhz, the fifo address set-up time is more than one ifclk cycle. ? at t = 1, the external master/peripheral must outputs the data value onto the data bus with a minimum set up time of t sfd before the rising edge of ifclk. ? at t = 2, slwr is asserted. th e slwr must meet the set-up time of t swr (time from asserting the slwr signal to the rising edge of ifclk) and maintain a minimum hold time of t wrh (time from the ifclk edge to the deassertion of the slwr signal). if slcs signal is used, it must be asserted with slwr or before slwr is asserted. (i.e., the slcs and slwr signals must both be asserted to start a valid write condition). ? while the slwr is asserted, data is written to the fifo and on the rising edge of the ifclk, the fifo pointer is incre- mented. the fifo flag will also be updated after a delay of t xflg from the rising edge of the clock. the same sequence of events are also shown for a burst write and are marked with the time indicators of t = 0 through 5. note: for the burst mode, slwr and slcs are left asserted for the entire duration of writi ng all the required data values. in this burst write mode, once the slwr is asserted, the data on the fifo data bus is written to the fifo on every rising edge of ifclk. the fifo pointer is updated on each rising edge of ifclk. in figure 10-20 , once the four bytes are written to the fifo, slwr is deasserted. the short 4-byte packet can be committed to the host by asserting the pktend signal. there is no specific timing r equirement that needs to be met for asserting pktend signal with regards to asserting the slwr signal. pktend can be asserted with the last data value or thereafter. the only requirement is that the set-up time t spe and the hold time t peh must be met. in the scenario of figure 10-20 , the number of data values committed includes the last value written to the fi fo. in this example, both the data value and the pktend signal are clocked on the same rising edge of ifclk. pktend can also be asserted in subse- quent clock cycles. the fifo addr lines should be held constant during the pktend assertion. although there are no specific timing requirement for the pktend assertion, there is a sp ecific corner case condition that needs attention while usin g the pktend to commit a one byte/word packet. additional timing requirements exists when the fifo is configured to operate in auto mode and it is desired to send two packets: a full packet (full defined as the number of bytes in the fifo meeting the level set in autoinlen register) committed automatically followed by a short one byte/word packet committed manually using the pktend pin. in this case, the external master must make sure to assert the pktend pin at least one clock cycle after the rising edge that caused the last byte/word to be clocked into the previous auto committed packet (the packet with the number of bytes equal to what is set in the au toinlen register). refer to figure 10-12 for further details on this timing. ifclk slwr flags data figure 10-20. slave fifo synchronous write sequence and timing diagram [20] t swr t wrh t sfd t xflg t ifclk n >= t swr >= t wrh n+3 pktend n+2 t xflg t sfa t fah t spe t peh fifoadr slcs t sfd t sfd t sfd n+1 t fdh t fdh t fdh t fdh t=0 t=1 t=2 t=3 t sfa t fah t=1 t=0 t=2 t=5 t=3 t=4
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 52 of 60 10.17.3 sequence diagram of a single and burst asynchronous read figure 10-21 diagrams the timing relationship of the slave fifo signals during an asynchronous fifo read. it shows a single read followed by a burst read. ? at t = 0 the fifo address is stable and the slcs signal is asserted. ? at t = 1, sloe is asserted. this results in the data bus being driven. the data that is driven on to the bus is previous data, it data that was in the fi fo from a prior read cycle. ? at t = 2, slrd is asserted. the slrd must meet the minimum active pulse of t rdpwl and minimum de-active pulse width of t rdpwh . if slcs is used then, slcs must be asserted before slrd is asserted (i.e., the slcs and slrd signals must both be asserted to start a valid read condition.) ? the data that will be driven, after asserting slrd, is the updated data from the fifo. this data is valid after a propa- gation delay of t xfd from the activating edge of slrd. in figure 10-21 , data n is the first valid data read from the fifo. for data to appear on the data bus during the read cycle (i.e.,slrd is asserted), sloe must be in an asserted state. slrd and sloe can also be tied together. the same sequence of events is also shown for a burst read marked with t = 0 through 5. note: in burst read mode, during sloe is assertion, the data bus is in a driven state and outputs the previous data. once slrd is asserted, the data from the fifo is driven on the data bus (s loe must also be asserted) and then the fifo poi nter is incremented. slrd flags sloe data figure 10-21. slave fifo asynchronous read sequence and timing diagram [20] t rdpwh t rdpwl t oeon t xfd t xflg n data (x) t xfd n+1 t xfd t oeoff n+3 n+2 t oeoff t xflg t sfa t fah fifoadr slcs driven t xfd t oeon t rdpwh t rdpwl t rdpwh t rdpwl t rdpwh t rdpwl t fah t sfa n t=0 t=0 t=1 t=7 t=2 t=3 t=4 t=5 t=6 t=1 t=2 t=3 t=4 nn sloe slrd fifo pointer n+3 fifo data bus not driven driven: x n not driven sloe n n+2 n+3 figure 10-22. slave fifo asynchrono us read sequence of events diagram slrd n n+1 slrd n+1 slrd n+1 n+2 slrd n+2 slrd n+2 n+1 sloe not driven sloe n n+1 n+1
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 53 of 60 10.17.4 sequence diagram of a single and burst asynchronous write figure 10-23 diagrams the timing relationship of the slave fifo write in an asynchronous mode. the diagram shows a single write followed by a burst write of 3 bytes and committing the 4-byte-short packet using pktend. ? at t = 0 the fifo address is applied, insuring that it meets the set-up time of t sfa . if slcs is used, it must also be asserted (slcs may be tied low in some applications). ? at t = 1 slwr is asserted. slwr must meet the minimum active pulse of t wrpwl and minimum de-active pulse width of t wrpwh . if the slcs is used, it must be in asserted with slwr or before slwr is asserted. ? at t = 2, data must be present on the bus t sfd before the deasserting edge of slwr. ? at t = 3, deasserting slwr will cause the data to be written from the data bus to the fifo and then increments the fifo pointer. the fifo flag is also updated after t xflg from the deasserting edge of slwr. the same sequence of events are shown for a burst write and is indicated by the timing marks of t = 0 through 5. note: in the burst write mode, once slwr is deasserted, the data is written to the fifo and then the fifo pointer is incremented to the next byte in the fifo. the fifo pointer is post incre- mented. in figure 10-23 once the four bytes are written to the fifo and slwr is deasserted, the short 4-byte packet can be committed to the host using the pktend. the external device should be designed to not assert slwr and the pktend signal at the same time. it should be designed to assert the pktend after slwr is deasserted and met the minimum deasserted pulse width. the fifoaddr lines are to be held constant during the pktend assertion. pktend slwr flags data figure 10-23. slave fifo asynchrono us write sequence and timing diagram [20] t wrpwh t wrpwl t xflg n t sfd n+1 t xflg t sfa t fah fifoadr slcs t wrpwh t wrpwl t wrpwh t wrpwl t wrpwh t wrpwl t fah t sfa t fdh t sfd n+2 t fdh t sfd n+3 t fdh t sfd t fdh t pepwh t pepwl t=0 t=2 t =1 t=3 t=0 t=2 t=1 t=3 t=6 t=9 t=5 t=8 t=4 t=7
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 54 of 60 11.0 ordering information table 11-1. ordering information ordering code package type ram size # prog i/os 8051 address /data busses ideal for battery powered applications cy7c68014a-128axc 128 tqfp ? lead-free 16k 40 16/8 bit cy7c68014a-100axc 100 tqfp ? lead-free 16k 40 ? cy7c68014a-56pvxc 56 sso p ? lead-free 16k 24 ? cy7c68014a-56lfxc 56 qfn ? lead-free 16k 24 ? cy7c68014a-56baxc 56 vf bga ? lead-free 16k 24 ? CY7C68016A-56lfxc 56 qfn ? lead-free 16k 26 ? ideal for non-battery powered applications cy7c68013a-128axc 128 tqfp ? lead-free 16k 40 16/8 bit cy7c68013a-128axi 128 tqfp ? lead-free (industrial) 16k 40 16/8 bit cy7c68013a-100axc 100 tqfp ? lead-free 16k 40 ? cy7c68013a-100axi 100 tqfp ? lead-free (industrial) 16k 40 ? cy7c68013a-56pvxc 56 sso p ? lead-free 16k 24 ? cy7c68013a-56pvxi 56 ssop ? le ad-free (industrial) 16k 24 ? cy7c68013a-56lfxc 56 qfn ? lead-free 16k 24 ? cy7c68013a-56lfxi 56 qfn ? lead-free (industrial) 16k 24 ? cy7c68015a-56lfxc 56 qfn ? lead-free 16k 26 ? cy7c68013a-56baxc 56 vf bga ? lead-free 16k 24 ? development tool kit cy3684 ez-usb fx2lp development kit reference design kit cy4611b usb 2.0 to ata/atapi reference design using ez-usb fx2lp
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 55 of 60 12.0 package diagrams the fx2lp is available in five packages: ? 56-pin ssop ? 56-pin qfn ? 100-pin tqfp ? 128-pin tqfp ? 56-ball vfbga package diagrams 51-85062-*c figure 12-1. 56-lead shrunk small outline package o56 0.80[0.031] 7.70[0.303] 7.90[0.311] a c 1.00[0.039] max. n seating plane n 2 0.18[0.007] 0.50[0.020] 1 1 0.08[0.003] 0.50[0.020] 0.05[0.002] max. 2 (4x) c 0.24[0.009] 0.20[0.008] ref. 0.80[0.031] max. pin1 id 0-12 6.45[0.254] 8.10[0.319] 7.80[0.307] 6.55[0.258] 0.45[0.018] 0.20[0.008] r. 8.10[0.319] 7.90[0.311] 7.80[0.307] 7.70[0.303] dia. 0.28[0.011] 0.30[0.012] 6.55[0.258] 6.45[0.254] 0.60[0.024] top view bottom view side view e-pad (pad size vary by device type) 51-85144-*d figure 12-2. 56-lead qfn 8 x 8 mm lf56a
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 56 of 60 package diagrams (continued) note: 1. jedec std ref ms-026 2. body length dimension does not include mold protrusion/end flash mold protrusion/end flash shall not exceed 0.0098 in (0.25 mm) per side 3. dimensions in millimeters body length dimensions are max plastic body size including mold mismatch 0.300.08 0.65 20.000.10 22.000.20 1.400.05 121 1.60 max. 0.05 min. 0.600.15 0 min. 0.25 0-7 (8x) stand-off r 0.08 min. typ. 0.20 max. 0.15 max. 0.20 max. r 0.08 min. 0.20 max. 14.000.10 16.000.20 0.10 see detail a detail a 1 100 30 31 50 51 80 81 e 1.00 ref. 0.20 min. seating plane 51-85050-*b figure 12-3. 100-pin thin plastic qu ad flatpack (14 x 20 x 1.4 mm) a100ra
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 57 of 60 package diagrams (continued) note: 1. jedec std ref ms-026 2. body length dimension does not include mold protrusion/end flash mold protrusion/end flash shall not exceed 0.0098 in (0.25 mm) per side 3. dimensions in millimeters body length dimensions are max plastic body size including mold mismatch 0.220.05 0.50 20.000.10 22.000.20 1.400.05 121 1.60 max. 0.05 min. 0.600.15 0 min. 0.25 0-7 (8x) stand-off r 0.08 min. typ. 0.20 max. 0.15 max. 0.20 max. r 0.08 min. 0.20 max. 14.000.10 16.000.20 0.08 see detail a detail a 128 e 1.00 ref. 0.20 min. seating plane 1 51-85101-*c figure 12-4. 128-lead thin plastic qu ad flatpack (14 x 20 x 1.4 mm) a128
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 58 of 60 13.0 pcb layout recommendations [24] the following recommendations should be followed to ensure reliable high-performance operation. ? at least a four-layer impedance controlled boards are re- quired to maintain signal quality. ? specify impedance targets (ask your board vendor what they can achieve). ? to control impedance, maintain trace widths and trace spac- ing. ? minimize stubs to minimize reflected signals. ? connections between the usb connector shell and signal ground must be done near the usb connector. ? bypass/flyback caps on vbus, near connector, are recom- mended. ? dplus and dminus trace leng ths should be kept to within 2 mm of each other in length, with preferred length of 20?30 mm. ? maintain a solid ground plane under the dplus and dmi- nus traces. do not allow the plane to be split under these traces. ? it is preferred is to have no vias placed on the dplus or dminus trace routing. ? isolate the dplus and dminus tr aces from all other signal traces by no less than 10 mm. 14.0 quad flat package no leads (qfn) package design notes electrical contact of the part to the printed circuit board (pcb) is made by soldering the leads on the bottom surface of the package to the pcb. hence, spec ial attention is required to the heat transfer area below the package to provide a good thermal bond to the circuit board. a copper (cu) fill is to be designed into the pcb as a thermal pad under the package. heat is transferred from the fx2lp through the device?s metal paddle on the bottom side of the package. heat from here, is conducted to the pcb at the t hermal pad. it is then conducted package diagrams (continued) top view pin a1 corner 0.50 3.50 5.000.10 bottom view 0.10(4x) 3.50 5.000.10 0.50 ?0.15mcab ?0.05 m c ?0.300.05(56x) a1 corner -b- -a- 1.0 max 0.160 ~0.260 0.080 c 0.45 seating plane 0.21 0.10 c -c- side view 5.000.10 5.000.10 reference jedec: mo-195c package weight: 0.02 grams e g h f d c b a 13 26 5 48 6 7 85 6 2 3 41 e g h f d c b a 001-03901-*b figure 12-5. 56 vfbga (5 x 5 x 1. 0 mm) 0.50 pitch, 0.30 ball bz56 note: 24. source for recommendations: ez-usb fx2?pcb design recommendations , http://www.cypress.com/cfuploads/support/app_notes/fx2_pcb.pdf and high speed usb platform design guidelines , http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf.
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 59 of 60 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. from the thermal pad to the pcb inner ground plane by a 5 x 5 array of via. a via is a plated through hole in the pcb with a finished diameter of 13 mil. the qfn?s metal die paddle must be soldered to the pcb?s thermal pad. solder mask is placed on the board top side over each via to resist solder flow into the via. the mask on the top side also minimizes outgassing during the solder reflow process. for further information on this package design please refer to the application note surface mount assembly of amkor?s microleadframe (mlf) technology . this application note can be downloaded from amkor?s w ebsite from the following url http://www.amkor.com/product s/notes_papers/mlf_appnote _0902.pdf. the application note provides detailed information on board mounting guidelines, soldering flow, rework process, etc. figure 14-1 below displays a cross-sectional area underneath the package. the cross section is of only one via. the solder paste template needs to be designed to allow at least 50% solder coverage. the thickness of the solder paste template should be 5 mil. it is recommended that ?no clean? type 3 solder paste is used for mounting the part. nitrogen purge is recommended during reflow. figure 14-2 is a plot of the solder mask pattern and figure 14-3 displays an x-ray image of the assembly (darker areas indicate solder). purchase of i 2 c components from cypress, or one of its sublicensed associated companies, conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided t hat the system conforms to the i 2 c standard specification as defined by philips. ez-usb fx2lp, ez-usb fx2 and renume ration are trademarks, and ez-usb is a registered trademark, of cypress semiconductor corporation. a ll product and company names mentioned in this document are the trademarks of their respective holders. 0.017? dia solder mask cu fill cu fill pcb material pcb material 0.013? dia via hole for thermally connecting the qfn to the circuit board ground plane. this figure only shows the top three layers of the circuit board: top solder, pcb dielectric, and the ground plane figure 14-1. cross-section of the area underneath the qfn package figure 14-2. plot of the solder mask (white area) figure 14-3. x-ray image of the assembly
cy7c68013a/cy7c68014a cy7c68015a/CY7C68016A document #: 38-08032 rev. *k page 60 of 60 document history page document title: cy7c68013a ez-usb fx2lp? usb micr ocontroller high-speed usb peripheral controller document number: 38-08032 rev. ecn no. issue date orig. of change description of change ** 124316 03/17/03 vcs new data sheet *a 128461 09/02/03 vcs added pn cy7c68015a throughout data sheet modified figure 1-1 to add ecc block and fix errors removed word ?compatible? where associated with i 2 c corrected grammar and formatting in various locations updated sections 3.2.1, 3.9, 3.11, table 3-9 , section 5.0 added sections 3.15, 3.18.4, 3.20 modified figure 3-5 for clarity updated figure 12-2 to match current spec revision *b 130335 10/09/03 kkv restored preliminary to header (had been removed in error from rev. *a) *c 131673 02/12/04 kku section 8.1 changed ?certified? to ?compliant? ta ble 9 -1 added parameter v ih_x and v il_x added sequence diagrams section 9.16 updated ordering information with lead-free parts updated registry summary section 3.12.4:example changed to column 8 from column 9 updated figure 10-3 memory write timing diagram updated section 3.9 (reset) updated section 3.15 ecc generation *d 230713 see ecn kku changed lead free marketing part numbers in ta ble 11 -1 as per spec change in 28-00054. *e 242398 see ecn tmd minor change: data sheet posted to the web, *f 271169 see ecn mon added usb-if test id number added usb 2.0 logo added values for isusp, icc, power dissipation, vih_x, vil_x changed vcc from + 10% to + 5% changed e-pad size to 4.3 mm x 5.0 mm changed pktend to flags output propagation delay (asynchronous interface) in table 10-14 from a max value of 70 ns to 115 ns *g 316313 see ecn mon removed cy7c68013a-56pvxct part availability added parts ideal for battery powered applications: cy7c68014a, CY7C68016A provided additional timing restrictions and requirement regarding the use of pketend pin to commit a short one byte/word packet subsequent to committing a packet automatically (when in auto mode). added min vcc ramp up time (0 to 3.3v) *h 338901 see ecn mon added information on the autoptr1/autoptr2 address timing with regards to data memory read/write timing diagram. removed tbd for min value of clock to fifo data output propagation delay (t xfd ) for slave fifo synchronous read changed table 11-1 to include part CY7C68016A-56lfxc in the part listed for battery powered applications added register gpcr2 in register summary *i 371097 see ecn mon added timing for strobing rd#/wr# signals when using portc st robe feature (section 10.5) *j 397239 see ecn mon removed xtalinsrc register from register summary. changed vcc margins to + 10% added 56-pin vfbga pin package diagram added 56-pin vfbga definition in pin listing added rdk part number to the ordering information table *k 420505 see ecn mon remove slcs from figure in section 10.10. removed indications that slrd can be asserted simultaneously with slcs in section 10.17.2 and section 10.17.3 added absolute maximum temperature rating for industrial packages in section 6.0 changed number of packages stated in the description in section 4.0 to five. added table 8-1 on thermal coefficients for various packages

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